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2023-11-07arm64: zynqmp: Remove address/size-cells from ams nodeMichal Simek
Remove unused address/size-cells which is also done upstream that's why this is pretty much sync patch with upstream. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/0ca8d8fe245ad7cb665f5333202d83f70acfc11f.1697115523.git.michal.simek@amd.com
2023-11-07Revert "arm64: zynqmp: Add power domain description for PL"Michal Simek
This reverts commit d59fac2f3f247470708a1aed1af96802a05e0e61. This power domain shouldn't be enabled by default. Power domain behavior should be handled on case by case basis. Adding this property to zynqmp.dtsi is breaking some suspend/resume cases that's why remove it from this file. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/7ed2a46383c6918fbbaca2d618459b1ee58f865c.1697115523.git.michal.simek@amd.com
2023-11-07arm64: zynqmp: Remove xlnx,zynqmp-aes nodeMichal Simek
AES can be discovered via firmware interface that's why remove node for it. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/eaf575a6ca92f8c10cefb447c08c1292025deb74.1697115523.git.michal.simek@amd.com
2023-11-07arm64: zynqmp: Use mdio node by vp-x-a2785-00-revA and vpk120-revAMichal Simek
All boards have been converted to use mdio node that's why move ethernet phys under mdio node too. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/6c60f5d29b9d9992bd0130fd263c8ed13cb8166c.1697115523.git.michal.simek@amd.com
2023-11-07arm64: zynqmp: Remove fclk driverMichal Simek
fclk will never go upstream that's why removing this node from DT. All PL (programmable logic) based IPs should handle clocks self without using this workaround. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/fbb8665b8a58dbe96349abfe5492a509939e165b.1697098930.git.michal.simek@amd.com
2023-11-07spi: cadence_ospi_versal: Add support for 64-bit addressVenkatesh Yadav Abbarapu
When 64-bit address is passed only lower 32-bit address is getting updated. Program the upper 32-bit address in the DMA destination memory address MSBs register. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20231011031515.4151-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-11-07drivers: firmware: Handle error case in the zynqmp_pm_featureVenkatesh Yadav Abbarapu
Unhandled error coming from xilinx_pm_request() but return value is not read back that's why getting sparse warning as below: warning: variable 'ret' set but not used [-Wunused-but-set-variable]. In case of error return the "ret" value. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20231011025647.17200-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-11-07arm64: versal_net: Disable the lock option for mini ospi and qspiVenkatesh Yadav Abbarapu
As mini configs are required only for flashing the images, so disabling the lock config which will save nearly 6KB of memory. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20231003031715.5343-4-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-11-07arm64: versal: Disable the lock option for mini ospi and qspiVenkatesh Yadav Abbarapu
As mini configs are required only for flashing the images, so disabling the lock config which will save nearly 6KB of memory. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20231003031715.5343-3-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-11-07mtd: spi-nor: Add spi flash lock config optionVenkatesh Yadav Abbarapu
Provide an explicit configuration option to disable default "lock" of any flash chip which supports locking. By disabling the lock config will save some amount of memory and also don't expose the lock functionality to the users i.e., via sf protect command. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20231003031715.5343-2-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-11-07serial: zynqmp: Fetch baudrate from dtb and updateAlgapally Santosh Sagar
The baudrate configured in .config is taken by default by serial. If change of baudrate is required then the .config needs to changed and u-boot recompilation is required or the u-boot environment needs to be updated. To avoid this, support is added to fetch the baudrate directly from the device tree file and update. The serial, prints the log with the configured baudrate in the dtb. The commit c4df0f6f315c ("arm: mvebu: Espressobin: Set default value for $fdtfile env variable") is taken as reference for changing the default environment variable. The default environment stores the default baudrate value, When default baudrate and dtb baudrate are not same glitches are seen on the serial. So, the environment also needs to be updated with the dtb baudrate to avoid the glitches on the serial. Also add test to cover this new function. Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20230921112043.3144726-3-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-11-07configs: Add support in Kconfig and convert for armada boardsAlgapally Santosh Sagar
Move the DEFAULT_ENV_IS_RW to Kconfig for easier configuration. Hence, add the CONFIG_DEFAULT_ENV_IS_RW config to the defconfig files to allow enabling them for armada boards. Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20230921112043.3144726-2-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-11-06Prepare v2024.01-rc2v2024.01-rc2Tom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-06configs: Resync with savedefconfigTom Rini
Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-06Merge branch '2023-11-06-assorted-changes'Tom Rini
- One new MIPS platform and a mailmap update
2023-11-06.mailmap: map Pali RohárHeinrich Schuchardt
Pali expressed that he does not want to receive mails relating to his past contributions. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2023-11-06bmips: Add Inteno XG6846 boardLinus Walleij
This adds support for the Inteno XG6846 board based on the Broadcom MIPS 6328 SoC. The default boot will read a uImage from flash and boot it. Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-11-06Merge tag 'u-boot-amlogic-20231106' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-amlogic - fixup to also enabled DFU RAM boot for libretech-ac - sm fix to bind child sm devices in the device tree - add missing A1 clocks for USB stack
2023-11-06Merge branch '2023-11-06-networking-updates'Tom Rini
- A few dhcp related improvements, be clearer to the user when we don't have a MAC address, assorted driver/phy improvements and new drivers.
2023-11-06ARM: configs: libretech-ac: enable USB_DFU like in meson64.hNeil Armstrong
USB_DFU was added in meson64.h but is missing in libretech-ac.h, fix this to enable DFU RAM boot for libretech-ac. Fixes 4aa027b3f8 ("configs: meson64: add alternate USB DFU boot target") Link: https://lore.kernel.org/r/20231102-libretech-ac-fix-dfu-v1-1-112379165028@linaro.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-11-06drivers: sm: bind child sm devices in the device treeDmitry Rokosov
One well-known sm child device that provides secure power control is the Secure Power Controller. This device utilizes SMC calls to communicate with power domains on the secure monitor side. Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com> Signed-off-by: Alexey Romanov <avromanov@salutedevices.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231101140500.9025-3-avromanov@salutedevices.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-11-06clk: a1: add new clocks for USB stackAlexey Romanov
Since we sync device tree with Linux, we have to add this clock definition for USB stack. Signed-off-by: Alexey Romanov <avromanov@salutedevices.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231101140500.9025-2-avromanov@salutedevices.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-11-05net: designware: add DMA offset awarenessBaruch Siach
Older DesignWare Ethernet MAC versions that this driver supports can only work with 32-bit DMA source/destination addresses. Some platforms have no physical RAM at the lowest 4GB address space. For these platforms the driver must translate DMA addresses to/from physical memory addresses. Call translation routines so that properly configured platforms can use the DesignWare Ethernet MAC. For platforms using device-tree this usually means adding dma-ranges property to the bus the device node is in. Signed-off-by: Baruch Siach <baruch@tkos.co.il>
2023-11-05net: eth-uclass: Improve error message when MAC is not foundFabio Estevam
While bringinp up a new board without the MAC fuses programmed, the following error message was observed: Error: ethernet@30bf0000 address not set. Improve the error message to make it clearer the reason of the failure. Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-11-05net: e1000: Drop e1000_eth_ids[]Bin Meng
e1000_eth_ids holds compatible strings for e1000 devices, but it is meaningless as e1000 is a PCI device and there is no such compatible string assigned to e1000 by the DT bindings community. Drop it. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-05net: Add option for tracing packetsSean Anderson
Add an option to trace all packets send/received. This can be helpful when debugging protocol issues, as the packets can then be imported into wireshark [1] and analyzed further. [1] https://www.wireshark.org/docs/wsug_html_chunked/ChIOImportSection.html Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-05net: phy: TI DP83869 fix invalid clock delay configurationFrank de Brabander
Setting the clock delay from the device tree settings rx-internal-delay-ps and tx-internal-delay-ps was broken: - The expected value in the device tree is suppose to be a delay in picoseconds, but the driver only allowed an array index. - Driver converted this array index to the actual delay in picoseconds and tried to apply this in the device register. This however is not a valid register value. The actual logic here was reversed, it converted an register representation of the delay to the device tree delay in picoseconds. Only when the internal delays were NOT configured in the device tree and they default value of 7 (=2000ps) was used, a valid value was loaded in the register. Signed-off-by: Frank de Brabander <debrabander@gmail.com>
2023-11-05net: eth-uclass: Setup ROM source only when ROM reading passesMichal Simek
There is no reason to setup ROM source if read_rom_hwaddr hook doesn't exist or reading mac address fails. It is ending up with confusion about mac address source. It is nicely visible if you put mac address to DT as local-mac-address = [ff ff ff ff ff ff]; but also save ethaddr to variables setenv -f ethaddr 02:18:31:7e:3e:01 Before this patch U-Boot prints that source is ROM Address in ROM is ff:ff:ff:ff:ff:ff Address in environment is 02:18:31:7e:3e:01 After that source is DT: Address in DT is ff:ff:ff:ff:ff:ff Address in environment is 02:18:31:7e:3e:01 Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-11-05net: add hifemac_mdio MDIO bus driver for HiSilicon platformYang Xiwen
It adds the driver for the internal MDIO bus of HIFEMAC Ethernet controller. It's based on the mainstream linux driver. Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
2023-11-05net: add hifemac Ethernet driver for HiSilicon platformYang Xiwen
It adds the driver for HIFEMAC Ethernet controller found on HiSilicon SoCs like Hi3798MV200. It's based on the mainstream linux driver, but quite a lot of code gets rewritten and cleaned up to adopt u-boot driver model. Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
2023-11-05net: mv88e6xxx: add Clause 45 supportRobert Marko
Marvell LinkStreet switches support Clause 45 MDIO on the internal bus. C45 read or writes require the register address to be written first to the SMI PHY Data register, and then a special C45 Write Address Register OP is used on the SMI PHY Register before making a C45 Read Data Register OP and being able to actually read the register. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
2023-11-05net: mv88e6xxx: use generic bitfield macros for MDIORobert Marko
Driver is currently defining the mask and bit shifting itself, there is no need for that as U-Boot has generic bitfield macros that help us achieve the same result but in a cleaner way. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
2023-11-05net: ftgmac100: Add reset controlDylan Hung
Add optional reset control, especially for the Aspeed SOC. For the hardware without a reset line, the reset assertion/deassertion will be skipped. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-11-05net: Get pxe config file from dhcp option 209Sean Edmond
Allow dhcp server pass pxe config file full path by using option 209 Signed-off-by: Sean Edmond <seanedmond@microsoft.com>
2023-11-05net: dhcp6: Fix OPT_BOOTFILE_PARAM parsingSean Edmond
RFC 5970 states that OPT_BOOTFILE_PARAM (option 60) can be multiple parameters that start with a 16-bit length field followed by the parameter. For example: [ param-len 1 (16-bits) ] [ parameter 1 (variable length) ] This fix ensure we're considering "param-len 1" in the parsing. Signed-off-by: Sean Edmond <seanedmond@microsoft.com>
2023-11-05net: dw_eth_qos: Add 64-bit addressingLey Foon Tan
Set upper 32bit address for DMA descriptors and buffer address to support 64-bit addressing. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-11-04Merge branch '2023-11-03-assorted-tegra-improvements'Tom Rini
- Assorted improvements for Tegra platforms
2023-11-03sysreset: implement PALMAS sysreset functionsSvyatoslav Ryhel
PALMAS PMIC family has embedded poweroff function used by some device to initiane device power off. Implement it as sysreset driver. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-11-03sysreset: implement TPS65910 sysreset functionsSvyatoslav Ryhel
TPS65910/TPS65911 PMICs have embedded power control functions used by some device to initiane device power off. Implement it as sysreset driver. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-11-03sysreset: implement TPS80031 sysreset functionsSvyatoslav Ryhel
TPS80031/TPS80032 PMICs have embedded power control functions used by some device to initiane device power off. Implement it as sysreset driver. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-11-03sysreset: implement MAX77663 sysreset functionsSvyatoslav Ryhel
MAX77663 PMIC has embedded poweroff function used by some device to initiane device power off. Implement it as sysreset driver. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-11-03arm: mach-tegra: enable sysreset driverSvyatoslav Ryhel
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-11-03sysreset: tegra: create arch specific sysreset driverSvyatoslav Ryhel
Tegra uses built in Power Management Controller (PMC) to perform CPU reset. Code to perform this was located in mach-tegra, so lest create DM driver to handle this. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-11-03power: regulator: tps65911: add regulator supportSvyatoslav Ryhel
The driver provides regulator set/get voltage enable/disable functions for TI TPS5911 PMIC. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-03power: pmic: tps65910: add TPS65911 PMIC supportSvyatoslav Ryhel
Add support to bind the regulators/child nodes with the pmic. Also adds the pmic i2c based read/write functions to access pmic registers. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-03power: regulator: tps80031: add regulator supportSvyatoslav Ryhel
The driver provides regulator set/get voltage enable/disable functions for TI TPS80031/TPS80032 PMICs. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-03power: pmic: add the base TPS80031 PMIC supportSvyatoslav Ryhel
Add support to bind the regulators/child nodes with the pmic. Also adds the pmic i2c based read/write functions to access pmic registers. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-03power: regulator: max77663: add regulator supportSvyatoslav Ryhel
The driver provides regulator set/get voltage enable/disable functions for MAXIM MAX77663 PMICs. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-11-03power: pmic: add the base MAX77663 PMIC supportSvyatoslav Ryhel
Add support to bind the regulators/child nodes with the pmic. Also adds the pmic i2c based read/write functions to access pmic registers. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-11-03power: regulator: palmas: fix ldoln and ldousb detectionSvyatoslav Ryhel
dev->driver_data will carry the tail of ldo if there is a number and if there is no number it will be an error code, anyway it will not be zero. This results in a wrong ldo regulator detection. To avoid this check for non-numerical ldo first and then manipulate dev->driver_data. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
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