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2025-01-14arm64: zynqmp: Add eeprom labels for System Controller dtsJonathan Stroud
Label all eeproms so we can open by label rather than a fixed i2c address. Signed-off-by: Jonathan Stroud <jonathan.stroud@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/878558c3c859599d29bc4ae2278baebf84b368e0.1736152966.git.michal.simek@amd.com
2025-01-14arm64: zynqmp: Enable iio-hwmon description only for SOMMichal Simek
Description is coming from SOM only that's why enable it only on SOM. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/08ee4ce2fe242905dd99cea2b87373b57d8fea91.1736152939.git.michal.simek@amd.com
2025-01-14arm64: zynqmp: Sync DTs with Linux v6.13-rc1Michal Simek
Sync zynqmp* DTS files with v6.13-rc1 Linux kernel including three patches from Sean: arm64: zynqmp: Enable AMS for all boards arm64: zynqmp: Expose AMS to userspace as HWMON arm64: zynqmp: Add thermal zones Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/06e466d64c9d8e718e2f06a76cc65d6da2a37a7b.1733996500.git.michal.simek@amd.com
2025-01-14arm64: zynqmp: add clock-output-names property in clock nodesNaman Trivedi
Replace underscores with hyphens in the clock node names as per dt-schema rule. Also, add clock-output-names property to all clock nodes, so that the resulting clock name do not change when clock node name is changed. Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com> Acked-by: Senthil Nathan Thangaraj <senthilnathan.thangaraj@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/1080e31393c3e1b49735b77e7ddc14d570b83222.1733991159.git.michal.simek@amd.com
2025-01-10rockchip: rk3588: Implement checkboard() to print SoC variantJonas Karlman
Implement checkboard() to print current SoC model used by a board, e.g. one of: SoC: RK3582 SoC: RK3588 SoC: RK3588J SoC: RK3588S SoC: RK3588S2 when U-Boot proper is running. U-Boot 2025.01-rc1 (Nov 10 2024 - 00:31:29 +0000) Model: Generic RK3588S/RK3588 SoC: RK3588S2 DRAM: 8 GiB Information about the SoC model and variant is read from OTP. Also update rk3588s-u-boot.dtsi to include OTP in U-Boot pre-reloc phase, where checkboard() is called. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Tested-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10rockchip: rk356x: Implement checkboard() to print SoC variantJonas Karlman
Implement checkboard() to print current SoC model used by a board, e.g. one of: SoC: RK3566 SoC: RK3566T SoC: RK3568 SoC: RK3568B2 SoC: RK3568J when U-Boot proper is running. U-Boot 2025.01-rc1 (Nov 10 2024 - 00:39:37 +0000) Model: Generic RK3566/RK3568 SoC: RK3568J DRAM: 8 GiB (effective 7.7 GiB) Information about the SoC model and variant is read from OTP. Also update rk356x-u-boot.dtsi to include OTP in U-Boot pre-reloc phase, where checkboard() is called. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Tested-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10rockchip: rk3588-nanopc-t6-lts: Add missing board -u-boot.dtsiJonas Karlman
The commit 7cec3e701940 ("rockchip: rk3588-nanopc-t6: Add support for NanoPC-T6 LTS") added support for the LTS variant of NanoPC T6. However, a board specific -u-boot.dtsi file was never added. Due to the missing -u-boot.dtsi file the LTS fdt included in the FIT is never tagged with bootph props. When ENV_IS_IN_SPI_FLASH is enabled, not enabled in defconfig, the env can successfully load from SPI flash on the non-LTS variant, something that does not work on the LTS variant due to missing bootph-some-ram props in the LTS fdt. Fix this by adding a LTS -u-boot.dtsi file that just include the non-LTS -u-boot.dtsi file. Reported-by: Ricardo Pardini <ricardo@pardini.net> Fixes: 7cec3e701940 ("rockchip: rk3588-nanopc-t6: Add support for NanoPC-T6 LTS") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10rockchip: rk3399-gru: Include pinctrl and regulators in SPLJonas Karlman
Add bootph props and enable related Kconfig options to include vital regulators in SPL. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10rockchip: rk3399-gru: Remove unused nodes from xPL control FDTJonas Karlman
The eMMC PHY and SPI flash is not used in all xPL phases. Change to no longer include emmc_phy and spi_flash in all xPL phases. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10rockchip: rk3399-gru: Include binman generated FIT in u-boot.rom imageJonas Karlman
The u-boot.rom image contain u-boot.img FIT instead of the FIT generated by binman for the u-boot-rockchip.bin image. Change to include the binman generated FIT for the u-boot.rom image. This change result in TF-A being included and the use sha256 instead of crc32 checksum in the u-boot.rom FIT. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10rockchip: rk3399-gru: Fix include of TPL in u-boot.rom imageJonas Karlman
The chromebook specific u-boot.rom image does not include TPL when building with TPL=y or ROCKCHIP_EXTERNAL_TPL=y. Fix this by adding rockchip-tpl and u-boot-tpl nodes to the mkimage node for the u-boot.rom binman image. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10rockchip: rk3399-gru: Use SYS_SPI_U_BOOT_OFFS value in offset propJonas Karlman
Use the offset configured with SYS_SPI_U_BOOT_OFFS Kconfig option instead of a hardcoded 0x40000 for the FIT payload offset. This has no intended impact as SYS_SPI_U_BOOT_OFFS=0x40000. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10rockchip: use OF_UPSTREAM for rk3066a/rk3188Johan Jonker
The device tree for rk3066a/rk3188 combined is now available in the /dts/upstream directory. Use imply OF_UPSTREAM to migrate all rk3066a/rk3188 boards. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10rockchip: Add support for Radxa ROCK 5CFUKAUMI Naoki
Radxa ROCK 5C[1] is a Rockchip RK3588S2 based single board computer. [1] https://radxa.com/products/rock5/5c Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10board: rockchip: add FriendlyElec NanoPi R3STianling Shen
The NanoPi R3S(as "R3S") is an open source platform with dual-Gbps Ethernet ports designed and developed by FriendlyElec for IoT applications. Specification: - Rockchip RK3566 - 2GB LPDDR4X RAM - optional 32GB eMMC module - SD card slot - 2x 1000 Base-T - 3x LEDs (POWER, LAN, WAN) - 2x Buttons (Reset, MaskROM) - 1x USB 3.0 Port - Type-C 5V 2A Power Signed-off-by: Tianling Shen <cnsztl@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10rockchip: rk3288-firefly: Fix slow Ethernet initializionJonas Karlman
For some reason the Ethernet PHY reset delay is set to 1 second, this cause an unneccecery long boot delay. Firefly-RK3288 use RTL8211 Ethernet PHY, datasheet list an initial 10ms delay and then a 30-76ms delay before accessing registers. Change to use 80ms delay instead of a full second to speed up Ethernet initializion in U-Boot. Also enable PHY_REALTEK, DM_ETH_PHY and PHY_GIGE to improve Ethernet PHY support in U-Boot. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10rockchip: rk3288-firefly: Migrate to OF_UPSTREAMJonas Karlman
The device tree for Firefly-RK3288 in dts/upstream can be used as-is by U-Boot, migrate board to use OF_UPSTREAM. Add chosen stdout-path prop to board u-boot.dtsi as it is missing in DT from dts/upstream. Also change to use the upstream power_led symbol. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10rockchip: rk3288-firefly: Include sdmmc regulator in SPLJonas Karlman
Add bootph props and enable related Kconfig options to include the sdmmc regulator in SPL. Also enable SPL_DM_SEQ_ALIAS to ensure aliases is handled correctly in SPL. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10rockchip: rk3288-firefly: Include required DT nodes in xPLJonas Karlman
Add bootph- props to emmc, sdmmc, uart and related pinctrl nodes to ensure devices and pinctrl can be used in xPL and U-Boot pre-reloc. Remove the explicit bootph-all prop from the pinctrl node, any bootph- prop will automatically be propagated to the pinctrl node. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10rockchip: rk3288-firefly: Sort u-boot.dtsi nodes alphabeticallyJonas Karlman
Sort the nodes in rk3288-firefly-u-boot.dtsi in alphabetical order. This has no intended change to board DT, this only rearrange nodes in preparation for future changes. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10rockchip: rk3288-firefly: Drop unused SPL_LED related codeJonas Karlman
The firefly-rk3288_defconfig build target does not enable the SPL_LED Kconfig option. Drop the unused SPL_LED related code and replace it with a default-state prop to ensure the LED driver enable the LED at U-Boot proper phase. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10rockchip: rk3399-rockpro64: Hook sysreset gpio to enable full resetPaul Kocialkowski
The reset mechanism used by Linux to reset the SoC is known to only partially reset the logic. A mechanism is implemented in rk3399_force_power_on_reset to use a GPIO connected to the PMIC's over-temperature (OTP) reset pin, which fully resets all logic. Hook the associated GPIO where the function expects it to enable this reset mechanism and avoid any possible side-effect of partially-reset units. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-01-10rockchip: rk3399-roc-pc: Hook sysreset gpio to enable full resetPaul Kocialkowski
The reset mechanism used by Linux to reset the SoC is known to only partially reset the logic. A mechanism is implemented in rk3399_force_power_on_reset to use a GPIO connected to the PMIC's over-temperature (OTP) reset pin, which fully resets all logic. Hook the associated GPIO where the function expects it to enable this reset mechanism and avoid any possible side-effect of partially-reset units. Without this patch, reading from the micro sd slot fails after a reset. With this mechanism, U-Boot is able to boot from it reliably. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-01-10rockchip: rk3288-miqi: Fix slow Ethernet initializionJonas Karlman
For some reason the Ethernet PHY reset delay is set to 1 second, this cause an unneccecery long boot delay. MiQi use RTL8211 Ethernet PHY, datasheet list an initial 10ms delay and then a 30-76ms delay before accessing registers. Change to use 80ms delay instead of a full second to speed up Ethernet initializion in U-Boot. Also enable PHY_REALTEK, DM_ETH_PHY and PHY_GIGE to improve Ethernet PHY support in U-Boot. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10rockchip: rk3288-miqi: Migrate to OF_UPSTREAMJonas Karlman
The device tree for mqmaker MiQi in dts/upstream can be used as-is by U-Boot, migrate board to OF_UPSTREAM. The change to use DT from dts/upstream will include minor changes and fixes related to work led and usb otg. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10rockchip: rk3288-miqi: Include sdmmc regulator in SPLJonas Karlman
Add bootph props and enable related Kconfig options to include the sdmmc regulator in SPL. Also enable SPL_DM_SEQ_ALIAS to ensure aliases is handled correctly in SPL. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10rockchip: rk3288-miqi: Include required DT nodes in xPLJonas Karlman
Add bootph- props to emmc, sdmmc, uart and related pinctrl nodes to ensure devices and pinctrl can be used in xPL and U-Boot pre-reloc. Remove the explicit bootph-all prop from the pinctrl node, any bootph- prop will automatically be propagated to the pinctrl node. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10rockchip: rk3288-miqi: Remove unused work led node from xPLJonas Karlman
The work led is not used in xPL on rk3288-miqi, remove bootph props from the work led node to exclude it from xPL control FDT. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10rockchip: rk3288-miqi: Sort u-boot.dtsi nodes alphabeticallyJonas Karlman
Sort the nodes in rk3288-miqi-u-boot.dtsi in alphabetical order. This has no intended change to board DT, this only rearrange nodes in preparation for future changes. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10rockchip: rk3288-tinker: Fix slow Ethernet initializionJonas Karlman
For some reason the Ethernet PHY reset delay is set to 1 second, this cause an unneccecery long boot delay. Tinker Board use RTL8211E or RTL8211F Ethernet PHY, datasheet list an initial 10ms delay and then a 30-76ms delay before accessing registers. Change to use 80ms delay instead of a full second to speed up Ethernet initializion in U-Boot. Also enable PHY_REALTEK, DM_ETH_PHY and PHY_GIGE to improve Ethernet PHY support in U-Boot. Before: 1,404,971 960,924 eth_common_init 2,438,830 1,033,859 eth_initialize 2,444,449 5,619 main_loop 2,445,153 704 cli_loop After: 1,404,987 960,710 eth_common_init 1,519,110 114,123 eth_initialize 1,524,734 5,624 main_loop 1,525,452 718 cli_loop Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10rockchip: rk3288-tinker: Migrate to OF_UPSTREAMJonas Karlman
The device tree for ASUS Tinker Board and S variant in dts/upstream can be used as-is by U-Boot, migrate board to OF_UPSTREAM. The change to use DT from dts/upstream will include minor changes and fixes related to leds and regulators. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10rockchip: rk3288-tinker: Include mmc nodes in pre-reloc for env loadJonas Karlman
Include mmc related nodes in U-Boot proper pre-reloc phase to ensure environment can be loaded from mmc devices. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10rockchip: rk3288-tinker: Drop unused vcc_sd regulator from SPLJonas Karlman
The sdmmc power come from vcc33_sd pmic regulator and not from the vcc_sd fixed regulator, as currently defined in the in-tree DT. Drop vcc_sd and the related gpio7 and sdmmc_pwr nodes from being included in SPL along with any related Kconfig option. Also enable SPL_DM_SEQ_ALIAS to ensure aliases is handled correctly in SPL. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10rockchip: rk3288-tinker: Only include required DT nodes in TPLJonas Karlman
Drop the unneeded bootph-all prop from dmc node, it is already defined in soc u-boot.dtsi. Remove booth-all prop from gpio7 node, this node is not needed in TPL. Adjust bootph props to include pinctrl related nodes for UART2. Remove the explicit bootph-all prop from the pinctrl node, any bootph- prop will automatically be propagated to the pinctrl node. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10rockchip: rk3288-tinker: Sort u-boot.dtsi nodes alphabeticallyJonas Karlman
Sort the nodes in rk3288-tinker u-boot.dtsi files in alphabetical order. This has no intended change to board DTs and only rearrange nodes in preparation for future changes. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10rockchip: rk3288: Fix bootph prop for vop nodesJonas Karlman
The vop nodes does not need to be included in xPL control FDT, they only need to be included at U-Boot proper pre-reloc phase. Change to use bootph-some-ram prop to fix this. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10rockchip: rk3288: Use rk3288.dtsi from dts/upstreamJonas Karlman
rk3288.dtsi from arch/arm/dts is almost identical to the rk3288.dtsi from dts/upstream, it differs only with a minor change in hdmi port nodes, something that does not affect U-Boot. Remove arch/arm/dts/rk3288.dtsi to use rk3288.dtsi from dts/upstream. Also drop gpio aliases from -u-boot.dtsi that has been part of rk3288.dtsi for some time. No functional change to board DTs is intended with this removal. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-12-31Merge patch series "Fix OSPI boot for J722S"Tom Rini
Prasanth Babu Mantena <p-mantena@ti.com> says: This series fixes OSPI boot for J722S. It contains fixes for DMSC communication, R5 regmap for ospi and dma specific overrides for ospi. Test log: https://gist.github.com/PrasanthBabuMantena/ad469dd09ab7263f85f87dadda46c86d Link: https://lore.kernel.org/r/20241218131341.2073823-1-p-mantena@ti.com
2024-12-31arm: dts: k3-j721e-beagleboneai: Move to OF_UPSTREAMUdit Kumar
Move to using OF_UPSTREAM config and thus using the devicetree subtree and remove unused device tree files. Signed-off-by: Udit Kumar <u-kumar1@ti.com> Acked-by: Sumit Garg <sumit.garg@linaro.org>
2024-12-31arm: dts: k3-am62p-sk-binman: add SE security variant buildsBryan Brattlof
The Texas Instruments Foundational Security (TIFS) firmware must match the security level configured on the SoC. To boot Security Enforced (SE) variants of the AM62Px, add another tiboot3 build which packages the Security Enforced (SE) firmware variant for AM62Px SoCs. Signed-off-by: Bryan Brattlof <bb@ti.com>
2024-12-31arm: dts: k3-j722s*: Add overrides specific to OSPIVaishnav Achath
OSPI Boot requires overrides specific to R5 and also to use DMA in R5 SPL stage the DM_TIFS needs to be used. Add the corresponding overrides for R5 SPL stage. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Signed-off-by: Prasanth Babu Mantena <p-mantena@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com>
2024-12-31arm: dts: k3-j722s-r5-evm: Fix DM2TIFS secproxy thread IDVaishnav Achath
Fix the DM2TIFS secureproxy thread ID as per the latest TISCI documentation for J722S. https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j722s/sec_proxy.html Fixes: fc2da3a3d0d3 ("arm: dts: Introduce J722S U-Boot dts files") Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Signed-off-by: Prasanth Babu Mantena <p-mantena@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com>
2024-12-31Merge patch series "Cumulative fixes and updates for MediaTek ethernet driver"Tom Rini
Weijie Gao <weijie.gao@mediatek.com> says: This patch series contains fixes and updates for mtk_eth driver. Link: https://lore.kernel.org/r/cover.1734406967.git.weijie.gao@mediatek.com
2024-12-31arm: dts: mt7629: fix sgmii clock selection for ethernetWeijie Gao
Setup correct parent of clock CLK_TOP_SGMII_REF_1_SEL to allow sgmiisys1 work correctly. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2024-12-29arm64: dts: renesas: Add R8A779G0 V4H remoteproc DT nodeMarek Vasut
Describe APMU controller as a remoteproc device capable of starting the Cortex-R52 cores in Renesas R8A779G0 V4H SoC DT. The APMU IP is in fact a power management unit capable of additional operations, but those are not used by U-Boot so far. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-29arm64: dts: renesas: Drop OF_UPSTREAM conversion remnantMarek Vasut
This DTC_FLAGS assignment is no longer necessary as all R-Car Gen2/Gen3/Gen4 platforms have been converted to OF_UPSTREAM and matching DTC_FLAGS assignment is present in dts/upstream/src/arm64/Makefile . Drop the remnant. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-29arm64: renesas: Add Renesas R-Car V4H SPL implementationMarek Vasut
Add support for building U-Boot SPL for Renesas R-Car Gen4 R8A779G0 V4H SoC. The SPL initializes the DBSC5 DRAM controller, RT-VRAM and loads and starts U-Boot proper on the Cortex-A76 core. The SoC BootROM can not boot the CA76 core directly, instead the SPL starts on the CR52 core which immediately brings up the CA76 core, which in turn starts executing the actual SPL. This is achieved by placing a tiny bit of precompiled Aarch32 code at the very beginning of the SPL. The code consists of some 32 instructions, uses APMU to configure CA76 start address to offset 0x80 Bytes from start of the SPL, and uses APMU to start the CA76 core. The code parts the CR52 core in an endless loop once the CA76 core got started. The 32 instructions are completely arbitrary number, so is the offset 0x80 Bytes from start of SPL, because 0x80 = 128 decimal and 128 / 4 bytes per instruction is 32 instructions. The 32 instructions turned out to be enough to started the CA76 and 0x80 is nicely aligned. Once the SPL completes hardware initialization, the SPL loads U-Boot proper. The u-boot.itb proper fitImage contains 64bit build on u-boot-nodtb.bin and a DT for R8A779G0 V4H White Hawk board and is generated by binman. The u-boot.itb is loaded from SPI NOR offset 0x80000. In order to install this setup on an existing R8A779G0 V4H White Hawk board, build using r8a779g0_whitehawk_defconfig, generate SPI NOR image flash.bin and write flash.bin to SPI NOR offset 0x0 . Finally, configure board MD pin switches according to the R8A779G0 V4H White Hawk board documentation for 40 MHz SPI NOR boot using DMA and restart the board. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-29arm64: dts: renesas: Add R8A779G0 V4H DBSC5 and RT-VRAM DT nodesMarek Vasut
Describe DBSC5 DRAM controller and RT-VRAM configuration interface as two new DT nodes in R-Car Gen4 R8A779G0 U-Boot DT extras file. This node is used by the U-Boot SPL for R8A779G0 SoC, where the DBSC5 and RT-VRAM drivers bind to these nodes and bring up the DRAM controller and RT-VRAM settings respectively, so U-Boot proper can be loaded into DRAM and started on Cortex A76 core. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-27board: gateworks: venice: rename GW7905 to GW7500Tim Harvey
The GW7905 was renamed to GW7500 before release. Change the various names in the dt files and references. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2024-12-25Merge tag 'v2025.01-rc5' into nextTom Rini
Prepare v2025.01-rc5
generated by cgit v1.2.3 (git 2.0.4) at 2025-11-09 20:34:21 +0000