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path: root/arch/arm/include/asm/arch-imx8m
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2021-04-08iMX8M: Add support to enable CONFIG_IMX_HABYe Li
Add some SOC level codes and build configurations to use HAB lib for CONFIG_IMX_HAB (secure boot), like adding the SEC_CONFIG fuse, enable fuse driver, CAAM clock function, and add CAAM secure RAM to MMU table. The FSL_CAAM is temporally not enabled for iMX8M when CONFIG_IMX_HAB is set, because we don't need the CAAM driver for SPL. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08imx8m: add regs used by CAAMPeng Fan
Add regs used by CAAM Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08arch: mach-imx: imx8m: fix unique_id read error for imx8mpPeng Fan
The value of Unique ID in uboot and kernel is different for iMX8MP: serial#=02e1444a0002aaff root@imx8mpevk:/sys/devices/soc0# cat soc_uid D699300002E1444A The reason is that Fuse Addresses of Unique ID of iMX8MP are 0x420 and 0x430. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Alice Guo <alice.guo@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-03-01ARM: imx: Add missing FEC ethernet quirk for MX8MMarek Vasut
The MX8M also contains a gigabit MAC, so define FEC_QUIRK_ENET_MAC. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2021-01-23imx8m: clock: add type of set_clk_eqosPeng Fan
Add type of set_clk_eqos to make it could be used by other files. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-01-23imx: imx8mp_evk: enable eth supportPeng Fan
Add board code to configure the network interface Add net defconfig Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-12-13dm: treewide: Rename ..._platdata variables to just ..._platSimon Glass
Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-17imx8mq: fix SSCG_PLL_REFCLK_SEL_xPeng Fan
Fix SSCG_PLL_REFCLK_SEL_x, the offset starts from 0, not 16 Reported-by: Coverity 3448860 Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2020-09-17imx8mq: fix FRAC_PLL_REFCLK_SEL_MASKPeng Fan
Coverity reported dead code, however it is FRAC_PLL_REFCLK_SEL_MASK was wrongly set. Reported-by: Coverity 10045172 Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2020-07-14imx8m: power down fused coresPeng Fan
For non-Quad SoCs, the fused cpu cores could be powered down in SPL to save power. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14drivers: ddr: imx Workaround for i.MX8M DDRPHY rank to rank issueOliver Chen
Add logic to automatically update umctl2's setting based on phy training CDD value for rank to rank space issue Acked-by: Ye Li <ye.li@nxp.com> Signed-off-by: Oliver Chen <Oliver.Chen@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14drivers: ddr: imx8mp: Add inline ECC feature supportSherry Sun
the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-18common: Drop linux/bitops.h from common headerSimon Glass
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10imx: regs: add more fuse bank structurePeng Fan
Add more fuse bank structure for use. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx8mm: clock: fix fracpll decode issueYe Li
The fracpll decoding is using the bit definitions for int pll. Most of them are same, but the CLKE bit is different. Fix the wrong CLKE_MASK for fracpll and correct all bit definitions in fracpll decoding. Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx8mq: Set ARM core clock directly from ARM PLLPeng Fan
For ARM core clock, there are two input branches, and can select via mux: one from ARM PLL directly, second from CCM A53 clock root. Currently we are using second branch. But IC confirmed the CCM A53 root signoff timing is 1Ghz, so we should switch to input from ARM PLL directly. This patch fixes the CORE SEL slice configuration and switch ARM clock to ARM PLL. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx8m: update clock root and fix core_selPeng Fan
Update clock root table to let it be easy to configure clock at very early stage. Also the core_sel mux parent should be A53 CLK root and ARM PLL. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08imx: imx8mp: add pin header filePeng Fan
Add pin header file for i.MX8MP Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08imx: imx8mp: add basic clockPeng Fan
i.MX8MP has similar architecture as i.MX8MN, but it has different clk root and index, so add that to make i.MX8MP could use the non-dm clock driver. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-07ddr: imx8m: Return error values from LPDDR4 trainingFrieder Schrempf
In cases when the same SPL should run on boards with i.MX8MM, that differ in DDR configuration, it is necessary to try different parameters and check if the training done by the firmware suceeds or not. Therefore we return the DDR training/initialization success to the upper layer in order to be able to retry with different settings if necessary. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2019-11-05imx8mn: add pin headerPeng Fan
Add pin header for i.MX8MN Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-05imx8m: add clk support for i.MX8MNPeng Fan
i.MX8MN has similar architecture with i.MX8MM, so it could reuse the clock code of i.MX8MM, but i.MX8MN has different CCM root configurations, so need a separate root entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-03imx: imx8mq: add init_nand_clkPeng Fan
Add init_nand_clk to enable gpmi nand clock. Since i.MX8MQ not use CCF, so we still use legacy mode to configure the clock. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: add clk support for i.MX8MMPeng Fan
Introduce clk implementation for i.MX8MM, including pll configuration, ccm configuration. Mostly will be done clk dm driver, but such as DRAM part, we still use non clk dm driver, because we have limited sram. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: restructure clock.hPeng Fan
i.MX8MQ and i.MX8MM use different analog pll design, but they share same ccm design. Add clock_imx8mq.h for i.MX8MQ keep common part in clock.h Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: add pin header for i.MX8MMPeng Fan
Add pin header file for i.MX8MM To IMX8MM_PAD_NAND_WE_B_USDHC3_CLK, IOMUX_CONFIG_SION needs to be selected. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: update imx-regs for i.MX8MMPeng Fan
i.MX8MM has similar architecture with i.MX8MQ, but it has totally different PLL design and register layout change. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: imx-regs: drop unused register definitionsPeng Fan
Drop unused register definitions and structures for i.MX8MQ Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx: add support for i.MX8MQ power domain controllerPatrick Wildt
Add support for the power domain controller that's used on the i.MX8MQ. This will be needed to be able to power on the PCIe controller. Bindings taken from Linux, driver implementation taken from the i.MX8 power domain controller and adjusted for the i.MX8M SoC. Signed-off-by: Patrick Wildt <patrick@blueri.se>
2019-06-11imx: define ARCH_MXC for i.MX8/8M/7ULPPeng Fan
Without this definition, fsl_esdhc will access reserved registers on i.MX chips, so define ARCH_MXC to fix it. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-01-01imx8m: ddr: removed unused macrosPeng Fan
Remove unused DDRC register macros. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-01drivers: ddr: introduce DDR driver for i.MX8MPeng Fan
Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-01imx: imx8m: add lpddr4 header filePeng Fan
Introduce lpddr4 header file Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-01imx: imx8m: clock refactor dram pll partPeng Fan
Refactor dram_pll_init to accept args to configure different pll freq. Introduce dram_enable_bypass and dram_disable_bypass Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-01imx: rename mx8m,MX8M to imx8m,IMX8MPeng Fan
Rename mx8m,MX8M to imx8m,IMX8M Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jon Nettleton <jon@solid-run.com>
generated by cgit v1.2.3 (git 2.0.4) at 2025-09-21 16:50:30 +0000