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Implement early TPS6586X PMIC rail configuration setting SM0 being
VDD_CORE_1.2V to 1.2 volts and SM1 being VDD_CPU_1.0V to 1.0 volts.
While those are PMIC power-up defaults the SoC might have been reset
separately with certain rails being left at lower DVFS states which
is e.g. the case upon watchdog reset while otherwise nearly idling.
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To create the soc environment variable we concatenate two strings
on the stack. So far, strcat has been used for the first string as
well as for the second string. Since the variable on the stack is
not initialized, the first strcat may not start using the first
entry in the character array. This then could lead to an buffer
overflow on the stack.
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Add iomux definitions for DSPI second instance.
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
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Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
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Add device tree files for Freescale Vybrid platform and
Toradex Colibri VF50, VF61 modules.
Device tree files are taken from upstream Kernel.
Removed the stuff which are not used/supported yet in U-Boot.
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
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The environment variable was called bootargsm4, which is somewhat
incongruent with the boot command name "m4boot". Rename the bootargs
environment variable for Cortex-M4 to m4bootargs.
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We do use PWM instance zero by default which is actually muxed for PWM
as primary function.
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Enable the display driver on Apalis T30. Unfortunately the PWM pin
muxing wasn't any good neither which made that display stay dark.
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On popular request enable the display driver on Colibri T30. A few
notes about some things encountered during porting: While analogue VGA
(e.g. via the on-carrier RAMDAC) worked just fine from the beginning
the EDT display flickered like crazy which turned out to be a pin
muxing issue. Unfortunately the PWM pin muxing wasn't any good neither
which made that display stay dark. Enjoy.
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On popular request make the display driver from T20 work on T30 as
well. Turned out to be quite straight forward. However a few notes
about some things encountered during porting: Of course the T30 device
tree was completely missing host1x as well as PWM support but it turns
out this can simply be copied from T20. The only trouble compiling the
Tegra video driver for T30 had to do with some hard-coded PWM pin
muxing for T20 which is quite ugly anyway. On T30 this gets handled by
a board specific complete pin muxing table. The older Chromium U-Boot
2011.06 which to my knowledge was the only prior attempt at enabling a
display driver for T30 for whatever reason got some clocking stuff
mixed up. Turns out at least for a single display controller T20 and
T30 can be clocked quite similar. Enjoy.
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Some firmwares running on the secondary core rely on UART pins
muxed at start time. Mux the Vybrid UART2 (which maps to Colibri
UART_B) at startup.
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Add support for ARM global timer. This allows to save the platform
wide PIT timer for other purposes such as MQX on the secondary
Cortex-M4 core.
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Allow to boot eCos, MQX and bare-metal firmwares to boot on the
secondary Cortex-M4. The boot code is equal for all those firmware
types, the argument register will be set to 0 and the code will
jump to the specified entry point directly.
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Move entry point is Thumb2 check just after reading the entry point
from the FIT image.
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Include vf610m4bootldr, a mini boot loader for the Cortex-M4 CPU
inside Freescale Vybrid SoC. The mini loader enables caches and
copies the pointer to the device tree from the platform specific
argument register (PERSISTENT_ARG1) to the Cortex-M4 r2 register,
where the Linux kernel expects the pointer. The mini loader hence
essentially takes over the parts of the m4boot command which can
not be done from the Cortex-A5 main CPU.
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Add m4boot command which allows to boot FIT images on the Cortex-M4
kernel. The command currently only supports FIT image, which allows
to provide entry point and load addresses for all boot artifacts.
Currently, the Cortex-M4 mini loader needs to be loaded manually
to Kernel loadaddr - 0x80 (e.g. 0x8f000000, if kernel is loaded at
0x8f000080).
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The ipu has two display interfaces. Make the used one a parameter
in struct display_info_t instead of using unconditionally DI0.
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Rename the serial loader boot mode to "serial". Also add an alias
for the ESDHC1 controller, which provides the standard MMC connection
for the Colibri SO-DIMM default pinout.
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Add IOMUX for the pad used as USB pen. This needs to be driven low for
the Iris and Viola boards where it is pulled up high by default. This is
required for the USB host functionality to work on these boards. Use the
board specific weak initialisation function, to drive the pin low which
would be called on "usb start".
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
[use switch statement to make port selection more obvious]
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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use
make colibri_imx6_defconfig
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Use for the industrial temperature range rated modules:
make apalis_imx6_it_defconfig
Use for the commercial temperature range rated modules:
make apalis_imx6_defconfig
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Add I2C support in order to subsequently allow disabling the PMIC sleep
mode on low supply voltage.
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Add LCD display support defaulting to VESA VGA resolution. Different
resolutions configurable via device-tree.
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Use toradex,colibri_t20 as the device-tree compatible node value rather
than toradex,t20 in accordance to our Apalis/Colibri T30 products.
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Add GPIO's typically required for display handling such as GPIO 45
(SO-DIMM 71, BL_ON) or GPIO 22 (SO-DIMM 59, PWM<A> for backlight).
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Inorder to use the pins as GPIO, apart from setting the alt-function,
pinmuxing need to be done, this patch adds pinmux entries of
few GPIOs.
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
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Add GPIO support to Freescale VF610
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
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The Vybrid SoC family has the same display controller unit (DCU)
like the LS1021A SoC. This patch adds platform data, pinmux defines
and clock control to enable the driver for Vybrid based boards too.
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Implement boot mode for Vybrid SoC. Boot mode selection works much
like the i.MX6 implementation. Provide a standard set of boot modes
for the two eSDHC instances and use the reserved mode to jump into
SoC's recovery mechanism, the serial downloader.
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Allow reading recovery mode (RCM) boot type from the boot information
table (BIT) written by the boot ROM (BR) to the IRAM.
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Move Kconfig sourcing to top level as conceptually it does not make
much sense to source it from a particular board especially as sourcing
it multiple time is completely discouraged as it would lead to the
following warning message:
board/toradex/common/Kconfig:29:warning: choice value used outside its
choice group
board/toradex/common/Kconfig:32:warning: choice value used outside its
choice group
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Migrating our BSPs towards mainline U-Boot I noticed it suddenly booting
slower. With mainline Linux I noticed about a 1 to 2 second increase
while booting downstream L4T takes 10 to 15 seconds longer!
This reverts commit 858530a8c0a7ce7e573e513934804a00d6676813.
Conflicts:
drivers/serial/Makefile
(cherry picked from commit 752aae30a791326581efafbb761c0cebaba8d3ea)
Conflicts:
drivers/serial/serial_tegra.c
include/configs/tegra-common.h
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Add writebcb command which creates a NAND Boot Configuration Block
(BCB) at the beginning of the active flash device. The BCB stores
the information for the SoC internal boot ROM where the application
with a valid IVT header can be found on the NAND device. The first
two argument of the command need an offset of the NAND device where
the primary and secondary application can be found.
Typically, U-Boot is the application which gets loaded by the boot
ROM. Hence, the offset address need to be the address where U-Boot
(u-boot.imx along with a 0x400 long prefix) is stored on the device.
At least one location is mandatory.
Currently only the FCB (Firmware Configuration Block) is written to
the device. The DBBT (Discovered Bad Block Table) is optional and
not created by writebcb currently.
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Add an additional target which prepends the u-boot.imx image with
0x400 padding bytes. On Vybrid, this is required for NAND boot
devices. The configuration CONFIG_IMX_NAND enables this image
for a board.
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This adds initial support for Colibri VF50/VF61 based on Freescale
Vybrid SoC.
- CPU clocked at 396/500 MHz
- DDR3 at 396MHz
- for VF50, use PLL2 as memory clock (synchronous mode)
- for VF61, use PLL1 as memory clock (asynchronous mode)
- Console on UART0 (Colibri UART_A)
- Ethernet on FEC1
- PLL5 based RMII clocking (E.g. No external crystal)
- UART_A and UART_C I/O muxing
- Boot from NAND by default
- USB host and client support
Tested on Colibri VF50/VF61 booting using serial loader over UART.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
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Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
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Enables caches which provides a rather huge speedup of the boot loader.
Also mark the on-chip RAM as cachable since this is the area U-Boot runs
from.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
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Vybrid product family consists of several rather similar SoC which
can be determined by softare during boot time. This allows use of
variable ${soc} for Linux device tree files. Detect VF5xx CPU's by
reading the CPU count register. We can determine the second number
of the CPU type (VF6x0) which indicates the presence of a L2 cache.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
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Enable the SCSC (Slow Clock Source Controller) and select the external
32KHz oscillator. This improves the accuracy of the RTC.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
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In order to avoid code duplication, move the DDR3 initialization to the
common place under imx-common. Currently ROW_DIFF and COL_DIFF can be
chosen from the board file. The JEDEC timings are specified using a
common ddr3_jedec_timings structure.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
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Add an error in known-bad case so that we don't produce broken and
hard to debug binaries.
Signed-off-by: Pavel Machek <pavel@denx.de>
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According to Gordon Henderson's WiringPi library, there are some more
Pi revision IDs out there. Add support for them.
http://git.drogon.net/?p=wiringPi;a=blob_plain;f=wiringPi/wiringPi.c;hb=5edd177112c99416f68ba3e8c6c4db6ed942e796
At least ID 0x13 is out in the wild:
Reported-by: Chee-Yang Chau <cychau@gmail.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
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Since commit 79d75d752717 (ARM: move -march=* and -mtune= options to
arch/arm/Makefile), all the Tegra boards are broken because the SPL
is built for ARMv7.
Insert Tegra-specific code to arch/arm/Makefile to set compiler
flags for an earlier ARM architecture.
Note:
The v1 patch for commit 79d75d752717 *was* correct when it was
submitted. Notice it was originally written for multi .config
configuration where Kconfig set CONFIG_CPU_V7/CONFIG_CPU_ARM720T for
Tegra U-Boot Main/SPL, respectively. But, until it was merged into
the mainline, commit e02ee2548afe (kconfig: switch to single .config
configuration) had been already applied there.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reported-by: Stephen Warren <swarren@nvidia.com>
Reported-by: Jan Kiszka <jan.kiszka@siemens.com>
Tested-by: Jan Kiszka <jan.kiszka@siemens.com>
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Patch e11c6c27 (arm: Allow lr to be saved by board code) introduced
a different method to return from save_boot_params(). The SPL support
for AXP has been pulled and changing to this new method is now
required for SPL to work correctly.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Luka Perkov <luka.perkov@sartura.hr>
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Work_92105 from Work Microwave is an LPC3250-
based board with the following features:
- 64MB or 128MB SDR DRAM
- 1 GB SLC NAND, managed through MLC controller.
- Ethernet
- Ethernet + PHY SMSC8710
- I2C:
- EEPROM (24M01-compatible)
- RTC (DS1374-compatible)
- Temperature sensor (DS620)
- DACs (2 x MAX518)
- SPI (through SSP interface)
- Port expander MAX6957
- LCD display (HD44780-compatible), controlled
through the port expander and DACs
This board has SPL support, and uses the LPC32XX boot
image format.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
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Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
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This driver only supports Driver Model, not legacy model.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
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Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
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The controller's Reed-Solomon ECC hardware is
used except of course for raw reads and writes.
It covers in- and out-of-band data together.
The SPL framework is supported.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
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