u-boot-toradex.git - U-Boot bootloader for Apalis and Colibri modules

Age	Commit message (Expand)	Author
2020-02-10	riscv: Remove unnecessary instruction	Sean Anderson
2020-02-10	riscv: Add option to print registers on exception	Sean Anderson
2020-02-10	riscv: Fix breakage caused by linker relaxation	Sean Anderson
2020-01-17	common: Move relocate_code() to init.h	Simon Glass
2019-12-10	riscv: add option to wait for ack from secondary harts in smp functions	Lukas Auer
2019-12-10	riscv: Fix clear bss loop in the start-up code	Rick Chen
2019-12-10	riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL	Rick Chen
2019-12-10	riscv: ax25: add SPL support	Rick Chen
2019-12-02	common: Move board_get_usable_ram_top() out of common.h	Simon Glass
2019-12-02	common: Move enable/disable_interrupts out of common.h	Simon Glass
2019-12-02	common: Move ARM cache operations out of common.h	Simon Glass
2019-12-02	common: Move some cache and MMU functions out of common.h	Simon Glass
2019-09-03	riscv: cache: use CCTL to flush d-cache	Rick Chen
2019-09-03	riscv: cache: Flush L2 cache before jump to linux	Rick Chen
2019-09-03	riscv: ax25: add imply v5l2 cache controller	Rick Chen
2019-09-03	riscv: update fix_rela_dyn	Marcus Comstedt
2019-08-26	riscv: support SPL stack and global data relocation	Lukas Auer
2019-08-26	riscv: add SPL support	Lukas Auer
2019-08-26	riscv: add run mode configuration for SPL	Lukas Auer
2019-08-15	riscv: Access CSRs using CSR numbers	Bin Meng
2019-05-18	CONFIG_SPL_SYS_[DI]CACHE_OFF: add	Trevor Woerner
2019-05-09	riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is ena...	Rick Chen
2019-05-09	riscv: Introduce CONFIG_XIP to support booting from flash	Rick Chen
2019-04-08	riscv: ax25: Andes specific cache shall only support in M-mode	Rick Chen
2019-04-08	riscv: ax25: Add platform-specific Kconfig options	Rick Chen
2019-04-08	riscv: hang if relocation of secondary harts fails	Lukas Auer
2019-04-08	riscv: do not rely on hart ID passed by previous boot stage	Lukas Auer
2019-04-08	riscv: add support for multi-hart systems	Lukas Auer
2019-04-08	riscv: save hart ID in register tp instead of s0	Lukas Auer
2019-04-08	riscv: delay initialization of caches and debug UART	Lukas Auer
2019-02-27	riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems	Anup Patel
2019-02-27	riscv: Rename cpu/qemu to cpu/generic	Anup Patel
2019-01-15	riscv: move the AX25-specific implementation of flush_dcache_all	Lukas Auer
2018-12-18	riscv: Save boot hart id to the global data	Bin Meng
2018-12-18	riscv: Return to previous privilege level after trap handling	Bin Meng
2018-12-18	riscv: Fix context restore before returning from trap handler	Bin Meng
2018-12-18	riscv: Move trap handler codes to mtrap.S	Bin Meng
2018-12-18	riscv: Do some basic architecture level cpu initialization	Bin Meng
2018-12-18	riscv: Update supports_extension() to use desc from cpu driver	Bin Meng
2018-12-18	riscv: Remove non-DM version of print_cpuinfo()	Bin Meng
2018-12-18	riscv: Probe cpus during boot	Bin Meng
2018-12-18	riscv: qemu: Add platform-specific Kconfig options	Bin Meng
2018-12-18	riscv: ax25: Hide the ax25-specific Kconfig option	Bin Meng
2018-12-18	riscv: qemu: Create a simple-bus driver for the soc node	Bin Meng
2018-12-05	riscv: ax25-ae350: Pass dtb address to u-boot with a1 register	Rick Chen
2018-12-05	riscv: Add kconfig option to run U-Boot in S-mode	Anup Patel
2018-11-26	riscv: cache: Implement i/dcache [status, enable, disable]	Rick Chen
2018-11-26	riscv: save hart ID and device tree passed by prior boot stage	Lukas Auer
2018-11-26	riscv: do not blindly modify the mstatus CSR	Lukas Auer
2018-11-26	riscv: remove unused labels in start.S	Lukas Auer