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2024-04-18Revert "Merge patch series "pxe: Allow extlinux booting without CMDLINE ↵Tom Rini
enabled"" As reported by Jonas Karlman this series breaks booting on some AArch64 platforms with common use cases. For now the best path forward is to revert the series. This reverts commit 777c28460947371ada40868dc994dfe8537d7115, reversing changes made to ab3453e7b12daef47b9e91da2a2a3d48615dc6fc. Link: https://lore.kernel.org/u-boot/50dfa3d6-a1ca-4492-a3fc-8d8c56b40b43@kwiboo.se/ Signed-off-by: Tom Rini <trini@konsulko.com>
2024-04-10Merge patch series "pxe: Allow extlinux booting without CMDLINE enabled"Tom Rini
Simon Glass <sjg@chromium.org> says: This series is the culmanation of the current line of refactoring series. It adjusts pxe to call the booting functionality directly rather than going through the command-line interface. With this is is possible to boot using the extlinux bootmeth without the command line enabled. It also updates fastboot to do a similar thing.
2024-04-10treewide: Make arch-specific bootm code depend on BOOTMSimon Glass
Allow these functions to be compiled in when CONFIG_BOOTM is enabled, even if CONFIG_CMD_BOOTM is not. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Angelo Dureghello <angelo@kernel-space.org>
2024-04-09riscv: add backtrace supportBen Dooks
When debugging, it is useful to have a backtrace to find out what is in the call stack as the previous function (RA) may not have been the culprit. Since this adds size to the build, do not add it by default and avoid putting it in the SPL build if not needed. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Tested-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-02-28efi_loader: set IMAGE_DLLCHARACTERISTICS_NX_COMPATHeinrich Schuchardt
The IMAGE_DLLCHARACTERISTICS_NX_COMPAT flag marks an EFI binary where the following conditions are met [1]: * Executable and writable sections are separated. * The application does not run self-modifying code. * The application uses the EFI_MEMORY_ATTRIBUTE_PROTOCOL when loading executable code. * The application does not assume that all memory ranges are usable. * The stack is not expected to be executable. The only EFI binaries U-Boot provides that do not fulfill these requirements are the EFI app and the EFI payload. Once we have implemented separation of writable and executable memory in U-Boot we can use the IMAGE_DLLCHARACTERISTICS_NX_COMPAT flag to decide if we will load an EFI binary. [1] New UEFI CA memory mitigation requirements for signing https://techcommunity.microsoft.com/t5/hardware-dev-center/new-uefi-ca-memory-mitigation-requirements-for-signing/ba-p/3608714 Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-29riscv: separate .data and .text sections of EFI binariesHeinrich Schuchardt
EFI binaries should not contain sections that are both writable and executable. Separate the RX .text section from the RW .data section Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-29riscv: page align EFI binary sectionHeinrich Schuchardt
Change the alignment of the relocation code in EFI binaries to match page boundaries. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-29riscv: conflicting SPDX license linker scriptsHeinrich Schuchardt
Fix conflicting SPDX license information in linker scripts introduced by commit 7215787c4ea4 ("SPDX: Convert single license tags to Linux Kernel style"). Fixes: 7215787c4ea4 ("SPDX: Convert single license tags to Linux Kernel style") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-27riscv: cache: support cache enable in SPL stageZong Li
The power gating feature of pl2 should be enabled as early as possible, it would be better to put it in SPL stage. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-12-21Merge patch series "Complete decoupling of bootm logic from commands"Tom Rini
Simon Glass <sjg@chromium.org> says: This series continues refactoring the bootm code to allow it to be used with CONFIG_COMMAND disabled. The OS-handling code is refactored and a new bootm_run() function is created to run through the bootm stages. This completes the work. A booti_go() function is created also, in case it proves useful, but at last for now standard boot does not use this. This is cmdd (part d of CMDLINE refactoring) It depends on dm/bootstda-working which depends on dm/cmdc-working
2023-12-21bootm: Adjust arguments of boot_os_fnSimon Glass
Adjust boot_os_fn to use struct bootm_info instead of the separate argc, argv and image parameters. Update the handlers accordingly. Few of the functions make use of the arguments, so this improves code size slightly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-21riscv: Add a reset_cpu() functionSimon Glass
The current do_reset() is called from a command context. Add a function which can be used from anywhere, as is done on ARM. Adjust do_reset() to call it. Note that reset_cpu() is normally provided by SYSRESET so make this declaration conditional on that being disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Chanho Park <chanho61.park@samsung.com> Tested-by: Chanho Park <chanho61.park@samsung.com>
2023-12-06riscv: andes: Fix enable register settings of PLICSWYu Chien Peter Lin
On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
2023-11-02riscv: allow resume after exceptionHeinrich Schuchardt
If CSRs like seed are readable by S-mode, may not be determinable by S-mode. For safe driver probing allow to resume via a longjmp after an exception. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-11-02riscv: Weakly define invalidate_icache_range()Samuel Holland
Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-10-24riscv: Remove common.h usageTom Rini
We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-10-19riscv: Add Zbb support for building U-BootYu Chien Peter Lin
This patch adds ISA string to the -march to generate zbb instructions for U-Boot binaries, along with optimized string functions introduced from Linux kernel. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-10-19riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategyRandolph
Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-10-04riscv: bootstage: correct bootstage_report guardChanho Park
Below warning can be occurred when CONFIG_BOOTSTAGE and !CONFIG_SPL_BOOTSTAGE. It should be guarded by using CONFIG_IS_ENABLED for SPL build. arch/riscv/lib/bootm.c:46:9: warning: implicit declaration of function 'bootstage_report' 46 | bootstage_report(); | ^~~~~~~~~~~~~~~~ | bootstage_error Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-10-02Merge branch 'next'Tom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-09-24common: Drop linux/printk.h from common headerSimon Glass
This old patch was marked as deferred. Bring it back to life, to continue towards the removal of common.h Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-09-05risc-v: implement DBCN write byteHeinrich Schuchardt
The DBCN extension provides a Console Write Byte call. Implement function sbi_dbcn_write_byte to invoke it. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-31event: Convert existing spy records to simpleSimon Glass
Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-07-12riscv: Rename SiFive CLINT to RISC-V ALINTBin Meng
As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
2023-07-12riscv: clint: Update the sifive clint ipi driver to support aclintBin Meng
This RISC-V ACLINT specification [1] defines a set of memory mapped devices which provide inter-processor interrupts (IPI) and timer functionalities for each HART on a multi-HART RISC-V platform. The RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, however the device tree binding is a new one. This change updates the sifive clint ipi driver to support ACLINT mswi device, by checking the per-driver data field of the ACLINT mtimer driver to determine whether a syscon based approach needs to be taken to get the base address of the ACLINT mswi device. [1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
2023-07-06riscv: andes_plicsw: Fix IPI during OpenSBI invocationYu Chien Peter Lin
On some AE350 boards, we need to explicitly initialize the priority registers to a non-zero value so the boot hart can instruct secondary harts to jump to OpenSBI. This patch also updates the information about PLICSW. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-03-06riscv: semihosting: replace inline assembly with assembly fileAndre Przywara
So far we used inline assembly to inject the actual instruction that triggers the semihosting service. While this sounds elegant, as it's really only about a few instructions, it has some serious downsides: - We need some barriers in place to force the compiler to issue writes to a data structure before issuing the trap instruction. - We need to convince the compiler to actually fill the structures that we use pointers to. - We need a memory clobber to avoid the compiler caching the data in those structures, when semihosting writes data back. - We need register arguments to make sure the function ID and the pointer land in the right registers. This is all doable, but fragile and somewhat cumbersome. Since we now have a separate function in an extra file anyway, we can do away with all the magic and just write that in an actual assembler. This is much more readable and robust. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Sean Anderson <sean.anderson@seco.com>
2023-02-10Correct SPL uses of LMBSimon Glass
This converts 9 usages of this option to the non-SPL form, since there is no SPL_LMB defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-01riscv: memcpy: check src and dst before copyRick Chen
Add src and dst address checking, if they are the same address, just return and don't copy data anymore. Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-12-29efi_loader: set IMAGE_FILE_LARGE_ADDRESS_AWAREHeinrich Schuchardt
For the 64bit EFI binaries that we create set the IMAGE_FILE_LARGE_ADDRESS_AWARE characteristic in the PE-COFF header to indicate that they can handle addresses above 2 GiB. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-12-08arch/riscv: add semihosting support for RISC-VKautuk Consul
We add RISC-V semihosting based serial console for JTAG based early debugging. The RISC-V semihosting specification is available at: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-11-03riscv: Rename Andes PLIC to PLICSWYu Chien Peter Lin
As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-10-20riscv: andes_plic.c: use modified IPI schemeYu Chien Peter Lin
The IPI scheme in OpenSBI has been updated to support 8-core AE350 platform, the plicsw configuration needs to be modified accordingly. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-09-29dm: core: Drop ofnode_is_available()Simon Glass
This function is also available as ofnode_is_enabled(), so use that instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29treewide: Drop bootm_headers_t typedefSimon Glass
This is not needed and we should avoid typedefs. Use the struct instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-26riscv: Introduce AVAILABLE_HARTSRick Chen
In SMP all harts will register themself in available_hart during start up. Then main hart will send IPI to other harts according to this variables. But this mechanism may not guarantee that all other harts can jump to next stage. When main hart is sending IPI to other hart according to available_harts, but other harts maybe still not finish the registration. Then the SMP booting will miss some harts finally. So let it become an option and it will be enabled by default. Please refer to the discussion: https://www.mail-archive.com/u-boot@lists.denx.de/msg449997.html Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-09-26spl: introduce SPL_XIP to configNikita Shubin
U-Boot and SPL don't necessary share the same location, so we might end with U-Boot SPL in read-only memory (XIP) and U-Boot in read-write memory. In case of non XIP boot mode, we rely on such variables as "hart_lottery" and "available_harts_lock" which we use as atomics. The problem is that CONFIG_XIP also propagate to main U-Boot, not only SPL, so we need CONFIG_SPL_XIP to distinguish SPL XIP from other XIP modes. This adds an option special for SPL to behave it in XIP manner and we don't use hart_lottery and available_harts_lock, during start proccess. Signed-off-by: Nikita Shubin <n.shubin@yadro.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-07-26zynqmp: Run board_get_usable_ram_top() only on main U-BootAshok Reddy Soma
With commit ce39ee28ec31 ("zynqmp: Do not place u-boot to reserved memory location"), the function board_get_usable_ram_top() is allocating MMU_SECTION_SIZE of about 2MB using lmb_alloc(). But we dont have this much memory in case of mini U-Boot. Keep these functions which use lmb under CONFIG_LMB so that they are compiled and used only when LMB is enabled. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/75e52def75f573e554a6b177a78504c128cb0c4a.1657183534.git.michal.simek@amd.com
2022-07-26arm: riscv: Remove additional ifdef from code guarded by CONFIG_IS_ENABLEDMichal Simek
CONFIG_OF_LIBFDT is used twice for guarding the same code. It is enough to do it once that's why remove additional ifdefs from arm and risc-v code. Fixes: 0c303f9a6628 ("image: Drop IMAGE_ENABLE_OF_LIBFDT") Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Link: https://lore.kernel.org/r/f8e3ff9124195cbd957874de9a65ef79760ef5e7.1657183634.git.michal.simek@amd.com
2022-04-06riscv: provide missing base extension functionsHeinrich Schuchardt
Provide library functions to read: * machine vendor ID * machine architecture ID * machine implementation ID Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-03-10event: Convert arch_cpu_init_dm() to use eventsSimon Glass
Instead of a special function, send an event after driver model is inited and adjust the boards which use this function. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-15efi_loader: fix SectionAlignment, FileAlignmentHeinrich Schuchardt
The alignment of sections in the EFI binaries generated by U-Boot is incorrect. According to the PE-COFF specification [1] the minimum value for FileAlignment is 512. If the value of SectionAlignment is less then the page size, it must equal FileAlignment. Let's set both values to 512 for the ARM and RISC-V architectures. [1] https://docs.microsoft.com/en-us/windows/win32/debug/pe-format Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-01-15riscv: revert Complete efi header for RV32/64Heinrich Schuchardt
EDK II refuses to load the EFI binaries created by U-Boot. The reason is an incorrect PE-COFF header. The number of data directories does not match NumberOfRvaAndSizes. This leads to a failed consistency check in PeCoffLoaderGetPeHeader(): SizeOfOptionalHeader - HeaderWithoutDataDir) != NumberOfRvaAndSizes * sizeof(DATA_DIRECTORY)) Fixes: 9afaeec6ef8b ("riscv: Complete efi header for RV32/64") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2021-11-08riscv: function to retrieve SBI implementation versionHeinrich Schuchardt
Provide function sbi_get_impl_version() to retrieve the SBI implementation version. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-10-13fdtdec: Support reserved-memory flagsThierry Reding
Reserved memory nodes can have additional flags. Support reading and writing these flags to ensure that reserved memory nodes can be properly parsed and emitted. This converts support for the existing "no-map" flag to avoid extending the argument list for fdtdec_add_reserved_memory() to excessive length. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2021-10-13fdtdec: Support compatible string list for reserved memoryThierry Reding
Reserved memory nodes can have a compatible string list to identify the type of reserved memory that they represent. Support specifying an optional compatible string list when creating these nodes. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2021-10-08image: Drop IMAGE_ENABLE_OF_LIBFDTSimon Glass
Add a host Kconfig for OF_LIBFDT. With this we can use CONFIG_IS_ENABLED(OF_LIBFDT) directly in the tools build, so drop the unnecessary indirection. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2021-10-07sysreset: provide SBI based sysreset driverHeinrich Schuchardt
Provide sysreset driver using the SBI system reset extension. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Samuel Holland <samuel@sholland.org>
2021-10-07riscv: Fix setting no-map in reserved memory nodesSamuel Holland
The no-map property is wrongly skipped if a no-map reserved memory node follows one without that property. Fix this by not remembering the absence of a no-map property across loop iterations. Fixes: d4ea649f179a ("riscv: Provide a mechanism to fix DT for reserved memory") Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2021-09-23lmb: riscv: Add arch_lmb_reserve()Marek Vasut
Add arch_lmb_reserve() implemented using arch_lmb_reserve_generic(). It is rather likely this architecture also needs to cover U-Boot with LMB before booting Linux. Reviewed-by: Rick Chen <rick@andestech.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Atish Patra <atish.patra@wdc.com> Cc: Leo <ycliang@andestech.com> Cc: Rick Chen <rick@andestech.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tom Rini <trini@konsulko.com>
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