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2020-12-13dm: treewide: Rename dev_get_platdata() to dev_get_plat()Simon Glass
Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass
We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: Remove uses of device_bind_offset()Simon Glass
This function is not needed since the standard device_bind() can be used instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: core: Rename device_bind() to device_bind_offset()Simon Glass
This function is not necessary anymore, since device_bind_ofnode() does the same thing and works with both flattree and livetree. Rename it to indicate that it is special. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-11-10x86: Avoid using hardcoded number of variable range MTRRs in mtrr_commit()Bin Meng
Since commit 29d2d64ed55f ("x86: Add support for more than 8 MTRRs"), the maximum number of variable range MTRRs was increased from 8 to 10. On the BayTrail platform there are only 8 variable range MTRRs. In mtrr_commit() it still uses MTRR_MAX_COUNT which caused a #GP during VESA video driver probe. It should have been updated to use dynamically probed number. This fixes the boot failure seen on Intel Minnow Max board. Fixes: 29d2d64ed55f ("x86: Add support for more than 8 MTRRs") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-11-06x86: Silence some logging statementsSimon Glass
Quite a few log_info() calls are included in the x86 code which should use log_debug() instead. Convert them to reduce unwanted output. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06x86: Set up Chrome OS to boot into developer modeSimon Glass
Set up a few fields necessarily to make Chrome OS boot without showing a firmware error. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06x86: Use CONFIG_CHROMEOS_VBOOT for verified bootSimon Glass
At present CONFIG_CHROMEOS is used to determine whether verified boot is in use. The code to implement that is not in U-Boot mainline. However, it is useful to be able to boot a Chromebook in developer mode in U-Boot mainline without needing the verified boot code. To allow this, use CONFIG_CHROMEOS_VBOOT to indicate that verified boot should be used, and CONFIG_CHROMEOS to indicate that the board supports Chrome OS. That allows us to define CONFIG_CHROMEOS on coral. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06x86: Show the interrupt pointer with 'irqinfo'Simon Glass
It is useful for this command to show the address of the interrupt table. Add support for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05x86: Don't bother clearing global NVSSimon Glass
The bloblist guarantees that blobs are zeroed so there is no need to do an additional memset(). Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05x86: Allow writing tables to failSimon Glass
At present write_tables() can fail but does not report this problem to its caller. Fix this by changing the return type. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05x86: apl: Add core init for the SoCSimon Glass
Set up MSRs required for Apollo Lake. This enables Linux to use the timers correctly. Also write the fixed MSRs for this platform. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05x86: Fix up driver names to avoid dtoc warningsSimon Glass
At present there are a lot of dtoc warnings reported when building chromebook_coral, of the form: WARNING: the driver intel_apl_lpc was not found in the driver list Correct these by using driver names that matches their compatible string. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-29x86: apl: Take advantage of the of-platdata parent supportSimon Glass
Now that parent devices are supported with of-platadata, we don't need the messy code to fix up the parent pointers and allocations on Apollo Lake. Put the code behind a condition. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-29x86: apl: Enable SPI flash in TPL with APL_SPI_FLASH_BOOTSimon Glass
At present, enabling CONFIG_APL_SPI_FLASH_BOOT does not build since SPI and SPI flash are not enabled for TPL. Add a condition to fix this and tidy up a build warning in the SPI-flash driver. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-06bloblist: Allow custom alignment for blobsSimon Glass
Some blobs need a larger alignment than the default. For example, ACPI tables often start at a 4KB boundary. Add support for this. Update the size of the test blob to allow these larger records. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: edison: Generate an image suitable for xFSTKSimon Glass
It is useful to be able to flash Edison directly without relying on the installed U-Boot being functional. Add a binman image for this. It includes a 'OSIP' header (which happens to look like an MBR / (Master-Boot Record), U-Boot binary and an environment. I am not able to find a specification for OSIP. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-09-25x86: Add support for more than 8 MTRRsSimon Glass
At present the mtrr command only support 8 MTRRs. Some SoCs have more than that. Update the implementation to support up to 10. Read the number of MTRRs dynamically instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25x86: apl: Check low-level init in FSP-S pre-initSimon Glass
If U-Boot is not running FSP-S it should not do the pre-init either. Add a condition to handle this. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: Notify the FSP of the 'end firmware' eventSimon Glass
Send this notification when U-Boot is about to boot into Linux, as requested by the FSP. Currently this causes a crash with the APL FSP, so leave it disabled for now. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: Sort the MTRR tableSimon Glass
At present the MTRR registers are programmed with the list the U-Boot builds up in the same order. In some cases this list may be out of order. It looks better in Linux to have the registers in order, so sort them, Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: cpu: Report address width from cpu_get_info()Simon Glass
Add support for this new field in the common code used by most x86 CPU drivers. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: apl: Drop unnecessary code in PMC driverSimon Glass
We don't have CONFIG_PCI in TPL but it is present in SPL, etc. So this code is not needed. Drop it, and fix a code-style nit just above. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: apl: Generate ACPI table for LPCSimon Glass
Add an ACPI table for the LPC on Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: apl: Generate CPU tablesSimon Glass
Add ACPI generation to the APL CPU driver. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: apl: Add support for hostbridge ACPI generationSimon Glass
Support generating a DMAR table and add a few helper routines as well. Also set up NHLT so that audio works. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: apl: Generate required ACPI tablesSimon Glass
Add support for generating various ACPI tables for Apollo Lake. Add a few S3 definitions that are needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: apl: Allow reading hostbridge base addressesSimon Glass
Add a few functions to permit reading of various useful base addresses provided by the hostbridge. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: Support Atom SoCs using SWSMISCI rather than the SWSCISimon Glass
Some Atom SoCs use SWSMISCI for SMI control. Add a Kconfig to select this. It is used on Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: acpi: Add common Intel ACPI tablesSimon Glass
Add various tables that are common to Intel CPUs. These functions can be used by arch-specific CPU code. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: Add a few common Intel CPU functionsSimon Glass
Add functions to query CPU information, needed for ACPI. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: acpi: Add a common routine to write WiFi infoSimon Glass
Intel WiFi chips can use a common routine to write the information needed by linux. Add an implementation of this. Enable it for coral. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: apl: Support writing the IntelGraphicsMem tableSimon Glass
This table is needed by the Linux graphics driver to handle graphics correctly. Write it to ACPI. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: acpi: Support external GNVS tablesSimon Glass
At present U-Boot puts a magic number in the ASL for the GNVS table and searches for it later. Add a Kconfig option to use a different approach, where the ASL files declare the table as an external symbol. U-Boot can then put it wherever it likes, without any magic numbers or searching. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: Add a config for the systemagent PCIEX regions sizeSimon Glass
Add a way to specify the required size for this region. This is used when generating ACPI tables. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-21Merge branch 'master' into nextTom Rini
Merge in v2020.10-rc5
2020-09-21x86: fsp: Replace e-mmc with emmc in devicetree bindingsWolfgang Wallner
The term eMMC is used inconsistently within the FSP devicetree bindings (e-mmc and emmc), especially for "emmc-host-max-speed" documentation and code disagree. Change all eMMC instances within the FSP bindings to consistently use "emmc". The term "emmc" is already used a lot within U-Boot, while "e-mmc" is only used in the FSP bindings. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct one typo in the commit message] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-07Merge branch 'remove-config-nr-dram-banks-v9-2020-08-26' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-marvell into next
2020-09-01x86: Introduce USE_EARLY_BOARD_INIT optionAndy Shevchenko
Introduce USE_EARLY_BOARD_INIT option and select it by the actual users. Cc: George McCollister <george.mccollister@gmail.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-08-26CONFIG_NR_DRAM_BANKS: Remove unreferenced code as its always definedStefan Roese
Since commit 86cf1c82850f ("configs: Migrate CONFIG_NR_DRAM_BANKS") & commit 999a772d9f24 ("Kconfig: Migrate CONFIG_NR_DRAM_BANKS"), CONFIG_NR_DRAM_BANKS is always defined with a value (4 is default). It makes no sense to still carry code that is guarded with "#ifndef CONFIG_NR_DRAM_BANKS" (and similar). This patch removes all these unreferenced code paths. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Pali Rohár <pali@kernel.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-08-03sf: Drop dm.h header file from spi_flash.hSimon Glass
This header file should not be included in other header files. Remove it and use a forward declaration instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03x86: call32: Append appropriate suffixesAndy Shevchenko
Assembler is not happy: arch/x86/cpu/call32.S: Assembler messages: arch/x86/cpu/call32.S:36: Warning: no instruction mnemonic suffix given and no register operands; using default for `retf' Fix this by adding appropriate suffixes to the assembler commands. Fixes: 6f92ed8f1abf ("x86: Add a way to call 32-bit code from 64-bit mode") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-08-03x86: sipi_vector: Append appropriate suffixesAndy Shevchenko
Assembler is not happy: arch/x86/cpu/sipi_vector.S: Assembler messages: arch/x86/cpu/sipi_vector.S:134: Warning: no instruction mnemonic suffix given and no register operands; using default for `cmp' arch/x86/cpu/sipi_vector.S:139: Warning: no instruction mnemonic suffix given and no register operands; using default for `bts' arch/x86/cpu/sipi_vector.S:157: Warning: no instruction mnemonic suffix given and no register operands; using default for `cmp' Fix this by adding appropriate suffixes to the assembler commands. Fixes: 45b5a37836d5 ("x86: Add multi-processor init") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-08-03arch: x86: apl: Update FSP parametersBernhard Messerklinger
Add missing parameters to support full configuration of the latest FSP MR6 release. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-03x86: apl: fsp_bindings: Add support for u64 parametersBernhard Messerklinger
Add FSP_UINT64 read support as preparation for FSP-M and FSP-S parameter update. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-28x86: Change how selection of ROMs worksSimon Glass
Most x86 boards build a u-boot.rom which is programmed into SPI flash. But this is not unique to x86. For example some rockchip boards can also boot from SPI flash. Also, at least on x86, binary blobs are sadly quite common. It is not possible to build a functional image without them, and U-Boot needs to know this at build time. Introduce a new CONFIG_HAS_ROM option which selects whether u-boot.rom is built and a new CONFIG_ROM_NEEDS_BLOBS option to indicate whether binary blobs are also needed. If they are not needed, it is safe to build the ROM always. Otherwise we still require the BUILD_ROM environment variable. For now this affects only x86, but future patches will enable this for rockchip too. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-25cpu: Convert the methods to use a const udevice *Simon Glass
These functions should not modify the device. Convert them to const so that callers don't need to cast if they have a const udevice *. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-24Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"Tom Rini
This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com>
2020-07-20cpu: Convert the methods to use a const udevice *Simon Glass
These functions should not modify the device. Convert them to const so that callers don't need to cast if they have a const udevice *. Signed-off-by: Simon Glass <sjg@chromium.org>
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