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The i.MX 7 detection taken from upstream U-Boot adds a new macro
MXC_CPU_MX7S. The downstream U-Boot still has one runtime occurence
which currently checks for MXC_CPU_MX7D only. Fix this SoC detection
to detect MXC_CPU_MX7S too.
Note: While the GPT timer is available on i.MX 7, it is currently
not configured (CONFIG_GPT_TIMER). Instead, the CPU internal
syscounter timer is currently used (CONFIG_SYSCOUNTER_TIMER).
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Remove code which does not change anything. This also synchronizes
this function with the upstream variant of it.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Just release TPS65911 GPIO1 (EN_CORE_DVFS_N) connected to TPS62362
VSEL1 to switch VDD_CORE back to boot set 1 defaulting to 1.200V.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Change file and other names resp. strings to apalis-tk1 rather than
apalis_tk1 due to upstream Linux kernel device tree maintainers no
longer allowing any underscores to be used in any such.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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This can be useful if the same U-Boot binary is used for boards
available with a i.MX 7Solo and i.MX 7Dual.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Read the number of cores in the fuses to distinguish between
the dual and solo versions.
Tested on a mx7d sabresd and on a mx7solo warp7.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit e25a0656bac63c5fcd20ef4313dc09c409fc512d)
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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The management data input/output (MDIO) requires open-drain,
i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
this feature. So to TO1.1, need to enable open drain by setting
bits GPR0[8:7] for TO1.1.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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In current design, if any peripheral was assigned to both A7 and M4,
it will receive ipg_stop or ipg_wait when any of the 2 platforms
enter low power mode. We will have a risk that, if A7 enter wait,
M4 enter stop, peripheral will have chance to get ipg_stop and ipg_wait
asserted same time.
There are 26 peripherals impacted by this IC issue:
SIM2(sim2/emvsim2)
SIM1(sim1/emvsim1)
UART1/UART2/UART3/UART4/UART5/UART6/UART7
SAI1/SAI2/SAI3
WDOG1/WDOG2/WDOG3/WDOG4
GPT1/GPT2/GPT3/GPT4
PWM1/PWM2/PWM3/PWM4
ENET1/ENET2
Software Workaround:
The solution is set M4 to a different domain with A core.
So the peripherals are not shared by them. This way requires
the uboot implemented the RDC driver and set the 26 IPs above to domain 0 only.
CM4 image will set the M4 to domain 1 only.
This patch enables the CONFIG_MXC_RDC for mx7d SABRESD board and ARM2 boards, and
setup the 26 IP resources to domain 0.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Add the peripherals/masters definitions and registers base addresses
for mx7d RDC. Enable the RDC driver by setting CONFIG_MXC_RDC.
Signed-off-by: Ye.Li <B37916@freescale.com>
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We can rely on finish bit for temperature reading for TO1.1.
Also introduce CHIP_REV_xx macros for 7D.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Updated regulator naming in device tree as discussed with Stefan
earlier.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Code mostly ported from imx-kobs-5.3.
MTD partitioning is set accordingly.
writebcb: Write Boot Control Block (FCB and DBBT)
writeboot: Write bootloadder
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Note that this input mux seems to be missing in the current
reference manual, but has been proven to be working on actual
hardware.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
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Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Introduce CONFIG_SERIAL_TAG_BOARD which removes the definition of
void get_board_serial(struct tag_serialnr *serialnr)
in order to allow its definition in board specific code.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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This reverts commit e7d4767331f1a2cbef61b4e89beb73731f267499.
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This reverts commit 3b548a3ddf03dcbb646912ef7bbdd3cdb2daf81a.
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Fixed the issue that mfgtool failed to download u-boot with plugin enabled.
The u-boot plugin common codes should not call rom___pu_irom_hwcnfg_setup
when using serial download mode.
rom___pu_irom_hwcnfg_setup will load the IVT2 image from boot media, but this
is invalid for USB serial download mode.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit b16ae36d2ae3fa9f536fec691a3e1bfa6f26a8d0)
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This piece of code is for mx7, we should not use
do_mx6_showclocks.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Need to check fuse bit 25 of bank 0 word 4 before initialize bee.
The bit: 0 means bee enabled, 1 means bee disabled.
If disabled, continuing initialize bee will cause system hang, so
need to check this bit before initialize bee.
Add macro to enable BEE in header file, default disabled.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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We meet reset failure on mx6ul 9x9 evk. The internal reset logic between MMDC and
functional modules seems relate with the issue.
Turn off the LCDIF to stop DDR access before reset to avoid this possible internal
reset problem.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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In current design, if any peripheral was assigned to both A7 and M4,
it will receive ipg_stop or ipg_wait when any of the 2 platforms
enter low power mode. We will have a risk that, if A7 enter wait,
M4 enter stop, peripheral will have chance to get ipg_stop and ipg_wait
asserted same time.
There are 26 peripherals impacted by this IC issue:
SIM2(sim2/emvsim2)
SIM1(sim1/emvsim1)
UART1/UART2/UART3/UART4/UART5/UART6/UART7
SAI1/SAI2/SAI3
WDOG1/WDOG2/WDOG3/WDOG4
GPT1/GPT2/GPT3/GPT4
PWM1/PWM2/PWM3/PWM4
ENET1/ENET2
Software Workaround:
The solution is set M4 to a different domain with A core.
So the peripherals are not shared by them. This way requires
the uboot implemented the RDC driver and set the 26 IPs above to domain 0 only.
CM4 image will set the M4 to domain 1 only.
This patch enables the CONFIG_MXC_RDC for mx7d SABRESD board and ARM2 boards, and
setup the 26 IP resources to domain 0.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Add the peripherals/masters definitions and registers base addresses
for mx7d RDC. Enable the RDC driver by setting CONFIG_MXC_RDC.
Signed-off-by: Ye.Li <B37916@freescale.com>
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There is narrow window that PRE driver is ready but GPU driver probe later,
and the later GPU driver turn on PU may cause 'PRE hang' issue. To simplify
thing, do not turn off PU in u-boot.
Signed-off-by: Robin Gong <b38343@freescale.com>
(cherry picked from commit 6b0787b726e2ff32210d742d93ecd3f4bb2ae402)
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Add disconnect_from_pc API which is used to disconnect the connection
with PC which is established at rom code.
Tested-by: Spring Zhang <b17931@freescale.com>
Tested-by: Zhang Sanshan <b51434@freescale.com>
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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Add disconnect_from_pc API which is used to disconnect the connection
with PC which is established at rom code.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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enable fastboot command: "fastboot reboot-bootloader"
After type this command, the board will reboot to bootloader mode.
Set ANDROID_FASTBOOT_BOOT flag in SNVS_LPGPR before reboot.
Signed-off-by: Zhang Sanshan <b51434@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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1. Replace the UDC driver with community's USB gadget d_dnl driver.
2. Integrate the FSL SD/SATA/NAND flash operations, since the GPT and
EFI partitions are not support by i.MX.
3. Add FDT support to community's android image.
4. Change the booti command to boota, due to the booti has been used for
ARM64 image boot.
5. Modify boota implementation to load ramdisk and fdt to their loading
addresses specified in boot.img header, while bootm won't do it for
android image.
6. Modify the android image HAB implementation. Authenticate the boot.img
on the "load_addr" for both SD and NAND.
7. Enable new configuration CONFIG_FSL_FASTBOOT for Freescale's fastboot
with relevant header file "fsl_fastboot.h". While disabling the
configuration, the community fastboot is used.
8. Use community's way to combine cmdline in boot.img and u-boot environment,
not overwrite the cmdline in boot.img
Signed-off-by: Ye.Li <B37916@freescale.com>
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Add missed Kconfig files for mx7d_12x12_ddr3_arm2 board.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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We should divide the 1000MHz ENET PLL clock by 10 in order to achieve
100MHz, so fix the divider accordingly.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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This reverts commit 2bc93d766dee5d5dc33035446f82622c4f1fb784.
After further investigation, find L2 prefetch offset setting of 0xF is not the
root cause for USB stress reboot failure. With the fix in USB driver,
and L2 prefetch offset setting of 0xF, the reboot stress test has passed 4-days
both on imx6q and imx6qp sabreauto board.
Signed-off-by: Robby Cai <r63905@freescale.com>
(cherry picked from commit 6e9282c2567b2820699fa55d2c6bf0ab78e992d6)
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Add MX6UL LPDDR2 ARM2 board BSP codes, supported peripherals:
SD1, eMMC(USDHC2), USB OTG1, I2C, ENET2, PMIC.
Due to a board issue, the SD1 only supports 1 bit bus width.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Since the 6ul does not enable the CONFIG_LDO_BYPASS_CHECK, but have
to use the set_wdog_reset function. Need to move the funciton out of
CONFIG_LDO_BYPASS_CHECK to resolve build issue.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Change L2 prefetch offset to 0 to make system stable.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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To resolve USB camera bandwidth issue, the patch sets recommended AQoS
setting from IC team value for peripheral and only on imx6qp.
The address is: 0xbb0608, the value is: 0x80000201
Signed-off-by: Ye.Li <B37916@freescale.com>
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Configure the PMIC_STBY_REQ pin as open drain 100K according to
the design team's requirement for the PMIC_STBY_REQ pin.
Signed-off-by: Bai Ping <b51503@freescale.com>
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1. There is conflict when building secure boot, because some common
codes for MPC are included by using same configuration. So modify the
makefile to get rid of them.
2. The 6UL arch config is missed in hab.h. Fix this issue by using
the CONFIG_ROM_UNIFIED_SECTIONS.
Signed-off-by: Ye.Li <B37916@freescale.com>
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There is a hole in shadow registers address map of size 0x100
between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX and iMX6UL.
Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses,
we should account for this hole in address space.
Similar hole exists between bank 14 and bank 15 of size
0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX.
Note: iMX6SL has only 0-7 banks and there is no hole.
Note: iMX6UL doesn't have this one.
When reading, we use register offset, so need to account for holes
to get the correct address.
When writing, we use bank/word index, there is no need to account
for holes, always use bank/word index from fuse map.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Add SION bit for all i2c pin mux settings.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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This patch is to support Bus Encryption Engine(BEE) for i.MX 6UL.
Supported feature:
1. SNVS key and soft key
2. CTR and ECB mode
3. Specify address region to bee.
Two commands are included:
bee init [key] [mode] [start] [end] - BEE block initial
"Example: bee init 1 1 0x80000000 0x80010000\n"
bee test [region]
"Example: bee test 1\n"
Mapping:
[0x10000000 - (0x10000000 + size - 1)] : [start - (start + size - 1)]
[0x30000000 - (0x30000000 + IRAM_SIZE - 1)] : [IRAM_BASE_ADDR -
(IRAM_BASE_ADDR + IRAM_SIZE - 1)]
Whatever start is, start - (start + size -1) will be fixed mapping to
0x10000000 - (0x10000000 + size - 1)
Since default AES region's protected size is SZ_512M, so
on mx6ul evk board, you can not simply run 'bee init', it will
overlap with uboot execution environment, you can use
'bee init 0 0 0x80000000 0x81000000'.
If want to use bee, Need to define CONFIG_CMD_BEE in board configuration
header file, since CONFIG_CMD_BEE default is not enabled.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Since there is another 9x9 package for mx6ul, modify the BSP names
of ddr3 arm2 board and evk board to add 14x14 package info.
Also modify the loaded dtb file to align with kernel.
After the change, the build target for mx6ul ddr3 arm2 board is:
mx6ul_14x14_ddr3_arm2_config
and the build target for mx6ul evk board is:
mx6ul_14x14_evk_config
Signed-off-by: Ye.Li <B37916@freescale.com>
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On mx7d 12x12 lpddr3 arm2 board, POR_B reset in uboot will fail stress
reset test, and hangs in rom code. Rom log buffer show thats wrong
hab_image_entry and runs into serial download mode. Also there is no
time delay reset circuit for this board.
We found when disable CONFIG_VIDEO, all seems fine. Actually,
only the following piece of code can make stress reset ok,
"
writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, ®s->hw_lcdif_ctrl1_clr);
while (--timeout) {
if (readl(®s->hw_lcdif_ctrl1) & LCDIF_CTRL1_VSYNC_EDGE_IRQ)
break;
udelay(1);
}
"
Here we use lcdif_power_down API which is better to shutdown lcdif same as
the way used in arch_preboot_os.
Implement reset_misc for mx7, since it does not hurt for others boards.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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On MX7D, boot rom can provide some boot information such as boot device,
arm freq, axi freq, etc. (see the structure below)
Offset Byte4 | Byte3 | Byte2 | Byte1
0x0 Reserved | Boot Device Type | Boot Device Instance | Reserved
0x4 ARM core frequency(in Hz)
0x8 AXI bus frequency(in Hz)
0x0C DDR frequency(in Hz)
0x10 GPT1 input clock frequency(in Hz)
0x14 Reserved
0x18
0x1C
The boot information can be accessed by get the pointer at 0x1E8. This patch
changes the u-boot to use the new approach. When manufacture boot, the info
recorded is the actual SD port, not the failed device.
Signed-off-by: Ye.Li <B37916@freescale.com>
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* Add mx7d_19x19_lpddr3_arm2 target board supprt
* Enable i2c, spinor, usb, usdhc, qspi, enet, uart
* Build targets
mx7d_19x19_lpddr3_arm2_defconfig
mx7d_19x19_lpddr3_arm2_eimnor_defconfig
- Set EIMNOR settings for Intel Sibley Asynchronous mode
- Set flash sector size for 256kb (erase block size)
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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The iomuxc structure has changed to add 0x4000 offset for i.MX6SX and UL,
so when using this structure to access gpr registers needs to change
the base address to IOMUXC_BASE_ADDR.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Get the Unique ID of the chip from the fuse TESTER0 and TESTER1.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Change MXC_CCM_CCGR6_I2C4_xx to MXC_CCM_CCGR6_I2C4_SERIAL_xx
Remove duplicated mxs_set_vadcclk
Correct enable_pll_video usage
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Add board code for mx6ul ddr3 arm2 board.
QSPI, USDHC, ENET, USB, VIDEO, SPINOR, EIMNOR
Add sd1, qspi and spinor boot support
DDR script is 1.02 version.
Signed-off-by: Fugang Duan <b38611@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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