Age | Commit message (Collapse) | Author |
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Due to an undefined pin muxing function being used for CAM_MCLK_PCC0
that pin got locked and did no more allow for the Linux kernel and/or
our GPIOConfig tool to make any further modifications.
On Apalis T30 this pin is used as camera master clock CAM1_MCLK which
was impossible to do due to it being locked while on Colibri T30 this
pin is just multiplexed with the SD/MMC card clock MM_CLK which is
tri-stated by default anyway.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Change file and other names resp. strings to apalis-tk1 rather than
apalis_tk1 due to upstream Linux kernel device tree maintainers no
longer allowing any underscores to be used in any such.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Regular HDA mode requires the TK1 SoC being the master to drive the
DAP1_BIT_CLK and DAP1_SYNC pins therefore do not tristate their
outputs. Further more despite the level shifter direction of those pins
being called Shift_CTRL_Dir_In[2] those need to be configured as output
for regular HDA mode.
Note: If connecting to a I2S codec operating in master mode (e.g. as on
our i.MX 6 designs) the later would have to be changed to inputs again.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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To properly reset a Colibri iMX7 the PMIC reset capabilities need
to be used.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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The i.MX 7Solo only has one USB controller. Do not enable USB_PEN
but return a -ENODEV return code instead. This allows "usb start"
to work properly on Colibri iMX7S modules.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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i.MX7D TO1.1 changes DDR retension mode control to IOMUXC_GPR,
add support to this change for LPSR which needs to exit from
DDR retension mode.
Signed-off-by: Anson Huang <Anson.Huang@freescale.com>
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U-Boot on Apalis iMX6 has a known problem:
Apparently Apalis iMX6 does not works with Gigabit switches...
Limiting speed to 10/100Mbps, and setting master mode, seems to
be the only way to have a successful PHY auto negotiation.
How to fix: Understand why Linux kernel do not have this issue.
However, the current work around did not take effect since the
generic phy config function (which gets called after the board
level work-around) reenabled gigabit advertisment again.
Use the newly introduced environment variable to disable gigabit
Ethernet advertisement.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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The four level shifter output enables Shift_CTRL_OE[0 to 2 and 4] were
wrongly pulled up therefore disabling the respective pin's input resp.
output capabilities.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Implement optional PCIe EvalBoard initialisation which properly reset the PLX
(now Avago) PEX 8605 PCIe switch plus PCIe devices on the Apalis Evaluation
carrier board.
Please note that you will have to enable the second PCIe port in the dts as well
e.g.:
diff --git a/arch/arm/dts/tegra30-apalis.dts b/arch/arm/dts/tegra30-apalis.dts
index be4f4d6..321c7d6 100644
--- a/arch/arm/dts/tegra30-apalis.dts
+++ b/arch/arm/dts/tegra30-apalis.dts
@@ -59,6 +59,7 @@
};
pci@2,0 {
+ status = "okay";
nvidia,num-lanes = <1>;
};
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Make sure the Intel i210 gigabit Ethernet controller gets properly enabled by
disabling DEV_OFF_N in the initialisation sequence.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Fix PCIe gigabit Ethernet initialisation by explicitly
controlling +V3.3_ETH provided by LDO9 and LDO10.
Note: For this to work an assembly option needs to be
patched on the current prototypes.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Newer U-Boot changed the DCD alignment with the effect that the
MMDCx_MDCTL reg/val pair moved 4 bytes.
Move away from a hardcoded offset and parse the IVT and DCD table
to find the correct location.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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Adding command availability check for update fusing command useful for
update scripts.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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Adding update fusing command to assist in updating modules to the fast
boot mode as per the following article on our developer website:
http://developer.toradex.com/knowledge-base/linux-booting#eMMC_Fast_Boot_Mode_ApalisColibri_iMX6
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Currently a divider of 6 has been used, leading to following NAND
Flash Controller (NFC) clocks:
VF61: 27.7 MHz (166.7MHz bus clock)
VF50: 22 MHz (132MHz bus clock)
The NAND Flash Memory used on VF50 allows to use clock speed of
up to 33MHz, while the Flash Memory of VF61 allows 50MHz. We can
use the same divider of 4 on both modules to configure the maximal
possible clock speeds:
VF61: 41.7 MHz
VF50: 33 MHz
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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Configure the Ricoh PMIC RN5T567 at startup to reset the board
without delay.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Cap product id to avoid issues with a yet unknown one.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Used during manufacturing for setting the boot fuses.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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While at it fix whitespace issue.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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While at it remove unusable boot modes from the list.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Add pinmux and I2C setup call to register the Colibri I2C bus.
The fourth (I2C4) instance is used for the I2C bus defined in the
standard Colibri pinout. Use i2c dev 3 to switch to this bus.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
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HW patch required. Connect RMII_CRS_DV - ENET1_RXC, remove R166
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Output 50MHz reference clock works, sending works but no reception.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Use get_ram_size() to autodetect up to 2Gbyte of RAM on rank 0.
If chips with two ranks would get stuffed one would have to set the size
of one rank in DDRC_ADDRMAP0.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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The Colibri iMX7 uses a different pmic
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Add empty callback now needed when CONFIG_LDO_BYPASS_CHECK is defined.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/8111e4d0cd81226899be637013048281e3c097b4
http://compass.freescale.net/livelink/livelink?func=ll&objId=234753630&objAction=browse&viewType=1
arik_r2_sabre_ddr3_528_1.13.inc is for sabre-AI
arik_r2_sdb_ddr3_528_1.13.inc is for sabresd
1.13<-1.12:
Change log:
1. Remove 20c4080
1.12<-1.10
Change log:
1. NoC register DDRCONF change to 0 which is compatible
for only CS0 is used on board
2. Change 2 values to compatible with our DDR aid script,
these two registers doesn’t have any effect on current system
tRPA = 0;
//this bit only used in DDR2 mode
tAOFPD/tAONPD=0x4;
//These register only works when MDPDC. SLOW_PD = 1 which is 0 in script
Test results:
One mx6qp-sdb and one mx6qp-ard board and one mx6qp-ard board passed
60 hours memtester stress teset.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit 5fb08a4dcc7b8478fc4236b90ad8dc2190cf94e7)
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According to the latest datasheet(Rev. B, 07/2015), the VDD_SOC_IN
standby voltage should be 1.05V and on i.MX6QP, we can use the PMIC
'APS' mode in standby. we add a 25mV margin to cover the IR drop and
board tolerance, so the standby voltage of VDD_SOC_IN should be
setting to 1.075V.
Signed-off-by: Bai Ping <b51503@freescale.com>
(cherry picked from commit 3c38fae6dafd3b90fae2598dcbedf6cb7aa6f6af)
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