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path: root/cpu/mpc85xx
AgeCommit message (Expand)Author
2009-10-07NAND boot support for P1 P2 RDB PlatformsPoonam Aggrwal
2009-10-07u-boot-2009.03-p2020rdb-RAMBOOT-support-over-SDCARD-bootDipen Dudhat
2009-10-07u-boot-2009.03-p2020rdb-CONFIG_FSL_ESDHC-for-eSDHC-clkDipen Dudhat
2009-10-07u-boot-2009.03-p2020rdb-Fixup-SDHC-clock-in-dts-MPC8536DSGao Guanhua
2009-10-07u-boot-2009.03-p2020rdb-Boot-from-SDcard-MPC8536DS-v2Jason Jin
2009-10-07u-boot-2009.03-p2020rdb-Support-of-P1-P2-processors-v2Poonam Aggrwal
2009-10-07u-boot-2009.03-p2020rdb-DDR-data-width-from-SVRPoonam Aggrwal
2009-10-07u-boot-2009.03-p2020rdb-Removed-CONFIG_NUM_CPUS-for-85xxPoonam Aggrwal
2009-03-09Fix mpc85xx ddr-gen3 ddr_sdram_cfg.Ed Swarthout
2009-02-19Coding style cleanup, update CHANGELOGWolfgang Denk
2009-02-1685xx: Add eSDHC support for 8536 DSAndy Fleming
2009-02-1632bit BUg fix for DDR2 on 8572Poonam_Aggrwal-b10812
2009-02-16mpc85xx: Add support for the P2020Srikanth Srinivasan
2009-02-1685xx: Fix how we map DDR memoryKumar Gala
2009-02-1685xx: Format cpu freq printing to handle 8 coresKumar Gala
2009-01-23Add secondary CPUs processor frequency for e500 coreHaiying Wang
2009-01-2385xx: Convert CONFIG_SYS_PCI*_IO_BASE to _IO_BUS for FSL boardsKumar Gala
2009-01-2385xx: Convert CONFIG_SYS_{PCI*,RIO*}_MEM_BASE to _MEM_BUS for FSL boardsKumar Gala
2009-01-13Change DDR tlb start entry to CONFIG param for 85xxHaiying Wang
2008-12-19mpc8[56]xx: Put localbus clock in sysinfo and gdTrent Piepho
2008-12-19mpc8568: Double local bus clock dividerTrent Piepho
2008-12-1985xx: Fix the boot window issueDave Liu
2008-12-19Set IVPR to kenrel entry point in second core boot pageHaiying Wang
2008-12-19mpc8xxx: LCRR[CLKDIV] is sometimes five bitsTrent Piepho
2008-12-19mpc8[56]xx: Put localbus clock in device treeTrent Piepho
2008-12-1985xx: Add support to populate addr map based on TLB settingsKumar Gala
2008-12-06Update U-Boot's build timestamp on every compilePeter Tyser
2008-12-0485xx: init gd as early as possibleKumar Gala
2008-12-0485xx: Fix relocation of CCSRBARKumar Gala
2008-12-0485xx: Add PORDEVSR_PCI1 definePeter Tyser
2008-12-0385xx: Add CPU 2 errata workaround to all 8548 boardsPeter Tyser
2008-11-09Moved initialization of QE Ethernet controller to cpu_eth_init()Ben Warren
2008-11-09Moved initialization of FCC Ethernet controller to cpu_eth_initBen Warren
2008-11-09Fix typo in cpu/mpc85xx/cpu.cBen Warren
2008-10-2485xx: Fix the incorrect register used for DDR erratum1Dave Liu
2008-10-2485xx: Add basic e500mc core supportKumar Gala
2008-10-2485xx: Use CONFIG_SYS_CACHELINE_SIZE instead of magic numberKumar Gala
2008-10-21Use strmhz() to format clock frequenciesWolfgang Denk
2008-10-18Merge 'next' branchWolfgang Denk
2008-10-1885xx if NUM_CPUS>1, print cpu numberEd Swarthout
2008-10-18Have u-boot pass stashing parameters into device treeAndy Fleming
2008-10-1885xx: Export invalidate_{i,d}cache and add flush_dcacheKumar Gala
2008-10-18rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD
2008-10-17Revert "85xx: Using proper I2C source clock divider for MPC8544"Kumar Gala
2008-10-0885xx: Using proper I2C source clock divider for MPC8544Wolfgang Grandegger
2008-10-07Fix the incorrect DDR clk freq reporting on 8536DSJason Jin
2008-10-0785xx: Remove setting of *cache-line-size in device treesKumar Gala
2008-09-09Fix printf errors under -DDEBUGAndrew Klossner
2008-09-0985xx: Ensure timebase is zero on secondary coresKumar Gala
2008-09-08Removed hardcoded MxMR loop value from upmconfig() for MPC85xx.Sergei Poselenov
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