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2010-01-26ppc: Loose GOT access in IRQJoakim Tjernlund
Using the GOT in IRQ handlers requires r14 to be -ffixed-r14. Avoid this by relocatate transfer_to_handler too. This will allow to free up r14 later on. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
2010-01-25mpc5xxx: Support CPU internal watchdog.Detlev Zundel
Signed-off-by: Detlev Zundel <dzu@denx.de>
2010-01-24mpc512x: Add display of reset status registerDetlev Zundel
Content of the RSR is put into gd early so we can output it together with the CPU info. The clearing of gd in board_init_f is redundant for this architecture as it is done in cpu_init_f so we remove it. Signed-off-by: Detlev Zundel <dzu@denx.de>
2010-01-23SPEAr : Adding basic SPEAr architecture support.Vipin KUMAR
SPEAr Architecture support added. It contains the support for following SPEAr blocks - Timer - System controller - Misc registers Signed-off-by: Vipin <vipin.kumar@st.com>
2010-01-23Kirkwood: Makefile cleanup- fixed ordering (cosmetic change)Prafulla Wadaskar
As per coding guidlines, it is good to maintain proper ordering in the makefiles. This was missed during initial coding, corrected here. This was discovered during orion5x code review Thanks to Albert Aribaud for this. Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
2010-01-23s5pc1xx: update cache routinesMinkyu Kang
Because of v7_flush_dcache_all is moved to omap3/cache.S and s5pc110 needs cache routines, update s5pc1xx cache routines. l2_cache_enable and l2_caceh_disable are moved from cache.c to cache.S and invalidate_dcache is modified for SoC specific. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2010-01-21mpc512x: Use in/out accessors for all registersDetlev Zundel
This is not only a cosmetic change as it fixes the real bug of board reset not working with the ELDK 4.2 toolchain. Signed-off-by: Detlev Zundel <dzu@denx.de>
2010-01-21Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk
2010-01-21ppc4xx: Allow setting a single SPD EEPROM address for DDR2 DIMMsFelix Radensky
On platforms where SPD EEPROM and another EEPROM have adjacent I2C addresses SPD_EEPROM_ADDRESS should be defined as a single element array, otherwise DDR2 setup code would fail with the following error: ERROR: Unknown DIMM detected in slot 1 However, fixing SPD_EEPROM_ADDRESS would result in another error: ERROR: DIMM's DDR1 and DDR2 type can not be mixed. This happens because initdram() routine does not explicitly initialize dimm_populated array. This patch fixes the problem. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Stefan Roese <sr@denx.de>
2010-01-21ppc4xx: Fix reporting of bootstrap options G and F on 460EX/GTFelix Radensky
Bootstrap options G and F are reported incorrectly (G instead of F and vice versa). This patch fixes this. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Stefan Roese <sr@denx.de>
2010-01-17Blackfin: add support for kgdbRobin Getz
Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-18kgdb: drop duplicate debugger_exception_handlerMike Frysinger
The debugger_exception_handler definition is the same for everyone, so use the common one now. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-18mpc5xxx/cpu_init.c: Convert to IO accessors.Detlev Zundel
Signed-off-by: Detlev Zundel <dzu@denx.de>
2010-01-17Merge branch 'master' of git://git.denx.de/u-boot-blackfinWolfgang Denk
2010-01-17PCIe, USB: Replace 'end point' references with 'endpoint'Peter Tyser
When referring to PCIe and USB 'endpoint' is the standard naming convention. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Remy Bohmer <linux@bohmer.net>
2010-01-17Blackfin: handle anomaly 05000257Robin Getz
Need to reload the loop counters to keep from corrupting hardware loops. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17Blackfin: keep hwtrace on CPLB missRobin Getz
Crashes rarely happen in the CPLB miss handler compared to the rest of U-Boot code, so disable hardware tracing when processing misses. This way a crash due to other functions will be shown properly. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17Blackfin: use new bfin read/write mmr helper funcsMike Frysinger
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17Blackfin: move watchdog config check to MakefileMike Frysinger
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17Blackfin: support boards with no external memoryMike Frysinger
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17Blackfin: re-architect initcodeMike Frysinger
The single initcode function was growing unwieldy, so split it up the distinct steps into their own function. This should making digesting the result much easier on people. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17Blackfin: move section length calculation to linker scriptMike Frysinger
The length of the sections is fixed at link time, so let the linker do the calculation rather than doing it ourselves at runtime. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-12Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk
2010-01-07mpc83xx: add support configure bus parkingHeiko Schocher
Add support to configure bus parking mode and master in bus arbitration configuration (ACR). Add this for the kmeter1 port: Configure bus arbiter with recommended values from Freescale to improve bus latency/throughput for application with intensive QuiccEngine activity. Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-01-07mpc83xx: spd_sdram.c: Disable memory controller before initializingStefan Roese
The memory controller could already be enabled, when spd_sdram() is called. This could be the case for example, when the SDRAM is initialized by the JTAG debugger. The "sync" after the register access via the accessor function is still needed, because the macro uses the sync before the real write is done. So until not all accesses are converted to using accessor functions, this sync still needs to be made "manually" here. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd.eu> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-01-05fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleaveDave Liu
In chip-select interleaving case, we also need set the ODT_RD_CFG and ODT_WR_CFG in cs1_config register. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05fsl-ddr: add override for the Rtt_WrDave Liu
Different boards may require different settings of Dynamic ODT (Rtt_Wr). We provide a means to allow the board specific code to provide its own value of Rtt_Wr. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05fsl-ddr: add the override for write levelingDave Liu
add the override for write leveling sampling and start time according to specific board. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05fsl-ddr: Fix power-down timing settingsDave Liu
1. TIMING_CFG_0[ACT_PD_EXIT] was set to 6 clocks, but It should be set to tXP parameter, tXP=max(3CK, 7.5ns) 2. TIMING_CFG_0[PRE_PD_EXIT] was set to 6 clocks, but It should be set to tXP (if MR0[A12]=1) else to tXPDLL parameter We are setting the mode register MR0[A12]='1' Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05ppc/p4080: Fix reporting of PME & FM clock frequenciesKumar Gala
We incorrectly had the sense of PME_CLK_SEL, FM1_CLK_SEL, FM2_CLK_SEL backwards so we report the wrong frequency. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05ppc/85xx: Map boot page guarded for MP bootKumar Gala
We already map the page cache-inhibited. There is no reason we shouldn't also be marking it guarded to prevent speculative accesses. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05p4080: add readback to bootpage translation windowDave Liu
We need to add the readback to bootpage translation LAW to make it effect. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05ppc/85xx: Make SPD DDR TLB setup code use dynamic entry allocationKumar Gala
Now that we track which TLB CAM entries are used we can allocate entries on the fly. Change the SPD DDR TLB setup code to assume we use at most 8 TLBs (or the number free, which ever is fewer). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05ppc/85xx: Add tracking of TLB CAM usageKumar Gala
We need to track which TLB CAM entries are used to allow us to "dynamically" allocate entries later in the code. For example the SPD DDR code today hard codes which TLB entries it uses. We can now make that pick entries that are free. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05ppc/8xxx: Remove is_fsl_pci_agentKumar Gala
All users of is_fsl_pci_agent have been converted to fsl_is_pci_agent that uses the standard PCI programming model to determine host vs agent/end-point. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-0585xx: Add support to set DPAA (data path) devices clock frequenciesKumar Gala
Set clock-frequency for Frame Manager 0/1 and Patter Match Engine on p4080. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05ppc/8xxx: Don't use pci_cfg on FSL_CORENET platformsKumar Gala
The FSL_CORENET platforms use a completely different means to determine which PCIe port is enabled as well as if its a host or agent/end-point. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-0585xx: Add support for e500mc cache stashingKumar Gala
The e500mc core supports the ability to stash into the L1 or L2 cache, however we need to uniquely identify the caches with an id. We use the following equation to set the various stash-ids: 32 + coreID*2 + 0(L1) or 1(L2) The 0 (for L1) or 1 (for L2) matches the CT field used be various cache control instructions. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-12-20USB Consolidate descriptor definitionsTom Rix
The header files usb.h and usbdescriptors.h have the same nameed structure definitions for usb_config_descriptor usb_interface_descriptor usb_endpoint_descriptor usb_device_descriptor usb_string_descriptor These are out right duplicates in usb.h usb_device_descriptor usb_string_descriptor This one has extra unused elements usb_endpoint_descriptor unsigned char bRefresh unsigned char bSynchAddress; These in usb.h have extra elements at the end of the usb 2.0 specified descriptor and are used. usb_config_descriptor usb_interface_descriptor The change is to consolidate the definition of the descriptors to usbdescriptors.h. The dublicates in usb.h are removed. The extra element structure will have their name shorted by removing the '_descriptor' suffix. So usb_config_descriptor -> usb_config usb_interface_descriptor -> usb_interface For these, the common descriptor elements are accessed now by an element 'desc'. As an example - if (iface->bInterfaceClass != USB_CLASS_HUB) + if (iface->desc.bInterfaceClass != USB_CLASS_HUB) This has been compile tested on MAKEALL arm, ppc and mips. Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2009-12-15Merge branch 'next' of ../nextWolfgang Denk
2009-12-09mpc83xx: boot time regression, move LCRR setup back to cpu_init_fPeter Korsgaard
Commit c7190f02 (retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields) moved the LCRR assignment to after relocation to RAM because of the potential problem with changing the local bus clock while executing from flash. This change unfortunately adversely affects the boot time, as running all code up to cpu_init_r can cause significant slowdown. E.G. on a 8347 board a bootup time increase of ~600ms has been observed: 0.020 CPU: e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz 0.168 RS: 232 0.172 I2C: ready 0.176 DRAM: 64 MB 1.236 FLASH: 32 MB Versus: 0.016 CPU: e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz 0.092 RS: 232 0.092 I2C: ready 0.096 DRAM: 64 MB 0.644 FLASH: 32 MB So far no boards have needed the late LCRR setup, so simply revert it for now - If it is needed at a later time, those boards can either do their own final LCRR setup in board code (E.G. in board_early_init_r), or we can introduce a CONFIG_SYS_LCRR_LATE config option to only do the setup in cpu_init_r. Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-12-08common: delete CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOULHeiko Schocher
There is more and more usage of printing 64bit values, so enable this feature generally, and delete the CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL defines. Signed-off-by: Heiko Schocher <hs@denx.de>
2009-12-085xxx, fdt: move fdt_fixup_memory() to cpu.c fileHeiko Schocher
u-boot updates, before starting Linux, the memory node in the DTS. As this is a "standard" feature, move this functionality to the cpu.c file for mpc5xxx and mpc512x processors. Signed-off-by: Heiko Schocher <hs@denx.de>
2009-12-07Merge branch 'master' into nextWolfgang Denk
Conflicts: lib_generic/zlib.c Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-12-07help: Correct syntax of nandecc help output.Robert P. J. Day
"nandecc" help output should not reproduce the command name, nor have a trailing newline. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2009-12-07trab: fix warning: implicit declaration of function 'disable_vfd'Wolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-12-05Merge branch 'master' into nextWolfgang Denk
Conflicts: board/esd/plu405/plu405.c drivers/rtc/ftrtc010.c Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-12-05Generic udelay() with watchdog supportIngo van Lil
According to the PPC reference implementation the udelay() function is responsible for resetting the watchdog timer as frequently as needed. Most other architectures do not meet that requirement, so long-running operations might result in a watchdog reset. This patch adds a generic udelay() function which takes care of resetting the watchdog before calling an architecture-specific __udelay(). Signed-off-by: Ingo van Lil <inguin@gmx.de>
2009-12-05i386: Final RelocationGraeme Russ
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-12-05i386: Remove inline asm symbols from .dynsymGraeme Russ
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
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