summaryrefslogtreecommitdiff
path: root/drivers/clk
AgeCommit message (Collapse)Author
2023-02-22clk: uniphier: Add missing USB SS-PHY clocksKunihiko Hayashi
The USB SS-PHY needs its own clock, however, some clocks don't have clock gates. Define missing clock entries for the PHY as reference clock. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-12clk: Allow clk_get_by_name() with NULL nameSamuel Holland
This allows devm_clock_get(dev, NULL) to work and get the first clock, which is common in code ported from Linux. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20230122000252.53642-1-samuel@sholland.org
2023-02-12clk: imx8mn: fix imx8mn_enet_phy_sels clocks listDario Binacchi
[backport from linux commit 2626cf67f20b28446dfc3a5b9493dd535cdb747b] According to the "Clock Root" table of the reference manual (document IMX8MNRM Rev 2, 07/2022): Clock Root offset Source Select (CCM_TARGET_ROOTn[MUX]) ... ... ... ENET_PHY_REF_CLK_ROOT 0xAA80 000 - 24M_REF_CLK 001 - SYSTEM_PLL2_DIV20 010 - SYSTEM_PLL2_DIV8 011 - SYSTEM_PLL2_DIV5 100 - SYSTEM_PLL2_DIV2 101 - AUDIO_PLL1_CLK 110 - VIDEO_PLL_CLK 111 - AUDIO_PLL2_CLK ... ... ... while the imx8mn_enet_phy_sels list didn't contained audio_pll1_out for source select bits 101b. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Acked-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20221219113127.528282-4-dario.binacchi@amarulasolutions.com
2023-02-12clk: imx: rename video_pll1 to video_pllDario Binacchi
[backport from linux commit bedcf9d1dcf88ed38731f0ac9620e5a421e1e9d6] Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the name used in the RM is video_pll. So, let's rename "video_pll1" to "video_pll" to be consistent with the RM and avoid misunderstandings. No functional changes intended. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Acked-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20221219113127.528282-3-dario.binacchi@amarulasolutions.com
2023-02-12clk: imx8mn: rename vpu_pll to m7_alt_pllDario Binacchi
[backport from linux commit a429c60baefd95ab43a2ce7f25d5b2d7a2e431df] The IMX8MN platform does not have any video processing unit (VPU), and indeed in the reference manual (document IMX8MNRM Rev 2, 07/2022) there is no occurrence of its pll. From an analysis of the code and the RM itself, I think vpu pll is used instead of m7 alternate pll, probably for copy and paste of code taken from modules of similar architectures. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Acked-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20221219113127.528282-2-dario.binacchi@amarulasolutions.com
2023-02-12clk: nuvoton: fix bug for calculate pll clockJim Liu
Fix bug for npcm7xx bmc calculate pll clock. PLLCON1 need to divide by 2. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Acked-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20221121091528.1351-1-JJLIU0@nuvoton.com
2023-02-10Correct SPL uses of SANDBOX_CLK_CCFSimon Glass
This converts 12 usages of this option to the non-SPL form, since there is no SPL_SANDBOX_CLK_CCF defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-09Correct SPL uses of CMD_CLKSimon Glass
This converts 7 usages of this option to the non-SPL form, since there is no SPL_CMD_CLK defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2023-02-02clk: renesas: rcar-gen3: Factor out CPG libraryHai Pham
R-Car V3U has a CPG different enough to not be a generic Gen3 CPG but similar enough to reuse code. Introduce a new CPG library, factor out the SD clock and RPC clock handling and hook them to the generic Gen3 CPG driver so we have an equal state. Based on Linux commit [1] and [2] by Wolfram Sang [1] 8bb67d87346a ("clk: renesas: rcar-gen3: Factor out CPG library") [2] 6f21d145b90f ("clk: renesas: cpg-lib: Move RPC clock registration to the library") Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Marek: - Add rcar_clk_* prefix to all functions - Rebase on changes to clk: renesas: Introduce and use rcar_clk_get_rate64_div_table function - Use u32_encode_bits/GENMASK bitfield ops
2023-02-02clk: renesas: Add R8A77970 SD0H/SD0 clocks for SDHIHai Pham
On R-Car V3M (AKA R8A77970), the SD0CKCR is laid out differently than on the other R-Car gen3 SoCs. Hence, new clock types are introduced respectively. Based on Linux commit 381081ffc294 ("clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI") by Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Marek: - Fix missing ~ in GENMASK(a, b), use clrsetbits_le32 instead - Do not modify r8a77970-cpg-mssr.c much, drop enum r8a77970_clk_types which is now part of common clock types in rcar-gen3-cpg.h instead
2023-02-02clk: renesas: Switch to new SD clock handlingHai Pham
The old SD handling code was huge and could not handle all the details which showed up on R-Car Gen3 SoCs meanwhile. It is time to switch to another design. Have SDnH a separate clock, use the existing divider clocks and move the errata handling from the clock driver to the SDHI driver where it belongs. Based on Linux series by Wolfram Sang, commit bb6d3fa98a41 ("clk: renesas: rcar-gen3: Switch to new SD clock handling") and commit e5f7e81ee430a ("mmc: renesas_sdhi: Parse DT for SDnH") Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Marek: - Add rcar_clk_* prefix to all functions - Fix missing ~ in GENMASK(a, b), use clrsetbits_le32 instead - Use DIV_ROUND_CLOSEST, else if parent clock = 199999992 and rate = 200000000, the divider would be 0 and table lookup would fail. - Turn rcar_clk_get_table_val into signed integer, so it can return 0 as a valid value and negative values as errors. - Make the code operate on correct clock and add comment which explains the reasoning behind it. - Rebase on changes to clk: renesas: Introduce and use rcar_clk_get_rate64_div_table function
2023-02-02clk: renesas: Handle E3/D3 RPCSRC clockHai Pham
The RPCSRC clock divider on R-Car D3 is very similar to the one on R-Car E3, but uses a different pre-divider for the PLL0 parent. Add a new macro to describe it, reusing the existing clock type for R-Car E3. As both E3/D3 RPCSRC clock divider are different from the rest of R-Car Gen3, keep the original implementation from Linux. Based on Linux commit 40745482eec8 ("clk: renesas: r8a774c0: Add RPC clocks") by Lad Prabhakar and 9d18f81b3535 ("clk: renesas: r8a77995: Add RPC clocks") by Geert Uytterhoeven. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Add D3 tweaks
2023-02-02clk: renesas: Introduce and use rcar_clk_get_rate64_div_table functionHai Pham
Introduce new helper function to handle clock type that uses clk_div_table struct. Based vaguely on Linux code. Make use of clk_div_table in RPC clocks handling. The E3/D3 RPCSRC need to be handled differently and will be addressed in subsequence patch. Based on Linux commit db4a0073cc82 ("clk: renesas: rcar-gen3: Add RPC clocks") by Sergei Shtylyov. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Marek: - Squash patches to avoid adding unused code: clk: renesas: Make use of clk_div_table in RPC clocks handling clk: renesas: Introduce rcar_clk_get_rate64_div_table function - Move the new code to the beginning of clk-rcar-gen3 to avoid tables mixed with code - Use rcar_ prefix for get_table_div function - Get rid of custom macros, use GENMASK. Use custom field_get implementation as the generic FIELD_GET does not support constant mask and u32_get_bits requires higher optimization level - Pass in the register bit mask instead of width/shift combination - Turn rcar_clk_get_rate64_div_table into s64, as it can return -EINVAL
2023-02-02clk: renesas: Convert Gen2/Gen3 clock tables to clk-provider struct ↵Marek Vasut
clk_div_table Replace custom local structure with matching one from clk-provider.h . No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02clk: renesas: Drop core param from gen3_clk_get_rate64_pll_mul_regMarek Vasut
Drop 'core' parameter from gen3_clk_get_rate64_pll_mul_reg() function as it is only used in debug print. No functional change except for the debug print, which is disabled by default. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02clk: renesas: Use pre-defined offset for RPC clocksHai Pham
Since commit f7b4e4c0949f ("clk: renesas: Synchronize R-Car Gen3 tables with Linux 5.12"), the custom macros for RPC clocks were dropped. Use pre-defined offset for RPC clocks, same as what Linux does, instead of retrieving it from the macros Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02clk: renesas: Add and enable CPG reset driverMarek Vasut
Add trivial reset driver extension to the CPG clock driver. The change turns current CPG UCLASS_CLK driver instance into an UCLASS_NOP proxy driver, which in turn binds both generic rcar3_clk UCLASS_CLK clock driver as well as generic rcar_rst UCLASS_RESET reset driver to the CPG DT node. This way, any other drivers which use the 'reset' DT property can now obtain valid reset handle backed by a reset driver. The clock tables have been updated to represent the CPG driver and only implement the generic CPG proxy driver bind call, which binds the clock and reset drivers. The DM_RESET is now enabled for all R-Car Gen3 platforms. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02clk: renesas: r8a7796: Add R8A77961 CPG/MSSR supportHai Pham
Add support for the R-Car M3-W+ (R8A77961) SoC. R-Car M3-W+ is very similar to R-Car M3-W (R8A77960), which allows for both SoCs to share a driver. Based on Linux commit 2ba738d56db4 ("clk: renesas: r8a7796: Add R8A77961 CPG/MSSR support") Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02clk: renesas: Rename CLK_R8A7796 to CLK_R8A77960Hai Pham
Rename CONFIG_CLK_R8A7796 for R-Car M3-W (R8A77960) to CONFIG_CLK_R8A77960, to avoid confusion with R-Car M3-W+ (R8A77961), which will use CONFIG_CLK_R8A77961. Based on Linux commit 92d1ebae9abf ("clk: renesas: Rename CLK_R8A7796 to CLK_R8A77960") Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02clk: renesas: Synchronize R8A774E1 RZ/G2H clock tables with Linux 6.1.7Marek Vasut
Synchronize R8A774E1 RZ/G2H clock tables with Linux 6.1.7, commit 21e996306a6afaae88295858de0ffb8955173a15 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02clk: renesas: Synchronize R8A774C0 RZ/G2E clock tables with Linux 6.1.7Marek Vasut
Synchronize R8A774C0 RZ/G2E clock tables with Linux 6.1.7, commit 21e996306a6afaae88295858de0ffb8955173a15 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02clk: renesas: Synchronize R8A774B1 RZ/G2N clock tables with Linux 6.1.7Marek Vasut
Synchronize R8A774B1 RZ/G2N clock tables with Linux 6.1.7, commit 21e996306a6afaae88295858de0ffb8955173a15 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02clk: renesas: Synchronize R8A774A1 RZ/G2M clock tables with Linux 6.1.7Marek Vasut
Synchronize R8A774A1 RZ/G2M clock tables with Linux 6.1.7, commit 21e996306a6afaae88295858de0ffb8955173a15 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02clk: renesas: Synchronize R8A779A0 V3U clock tables with Linux 6.1.7Marek Vasut
Synchronize R-Car R8A779A0 V3U clock tables with Linux 6.1.7, commit 21e996306a6afaae88295858de0ffb8955173a15 . Rename CLK_TYPE_R8A779A0_ to CLK_TYPE_GEN4_ to match the new clock tables. Add CLK_TYPE_GEN4_SD, CLK_TYPE_GEN4_RPC and CLK_TYPE_GEN4_RPCD2 macros and handling into Gen3 CPG core. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02clk: renesas: Synchronize R8A77995 D3 clock tables with Linux 6.1.7Marek Vasut
Synchronize R-Car R8A77995 D3 clock tables with Linux 6.1.7, commit 21e996306a6afaae88295858de0ffb8955173a15 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02clk: renesas: Synchronize R8A77990 E3 clock tables with Linux 6.1.7Marek Vasut
Synchronize R-Car R8A77990 E3 clock tables with Linux 6.1.7, commit 21e996306a6afaae88295858de0ffb8955173a15 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02clk: renesas: Synchronize R8A77980 V3H clock tables with Linux 6.1.7Marek Vasut
Synchronize R-Car R8A77980 V3H clock tables with Linux 6.1.7, commit 21e996306a6afaae88295858de0ffb8955173a15 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02clk: renesas: Synchronize R8A77965 M3-N clock tables with Linux 6.1.7Marek Vasut
Synchronize R-Car R8A77965 M3-N clock tables with Linux 6.1.7, commit 21e996306a6afaae88295858de0ffb8955173a15 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02clk: renesas: Synchronize R8A77960 M3-W and R8A77961 M3-W+ clock tables with ↵Marek Vasut
Linux 6.1.7 Synchronize R-Car R8A77960 M3-W and R8A77961 M3-W+ clock tables with Linux 6.1.7, commit 21e996306a6afaae88295858de0ffb8955173a15 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02clk: renesas: Synchronize R8A7795 H3 clock tables with Linux 6.1.7Marek Vasut
Synchronize R-Car R8A7795 H3 clock tables with Linux 6.1.7, commit 21e996306a6afaae88295858de0ffb8955173a15 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02clk: renesas: Add dummy SDnH clockHai Pham
Currently, SDnH is handled together with SDn. This caused lots of problems, so we want SDnH as a separate clock. Introduce a dummy SDnH type here which creates a fixed-factor clock with factor 1. That allows us to convert the per-SoC CPG drivers while keeping the old behaviour for now. A later patch then will add the proper functionality. Based on Linux series by Wolfram Sang: commit a31cf51bf6b4b ("clk: renesas: rcar-gen3: Add dummy SDnH clock"), commit 1abd04480866c ("clk: renesas: rcar-gen3: Add SDnH clock"), commit 63494b6f98f26 ("clk: renesas: r8a779a0: Add SDnH clock to V3U") Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Switch to gen3_clk_get_rate64
2023-02-02ARM: dts: rmobile: Synchronize DTs with Linux 6.1.7Marek Vasut
Synchronize R-Car device trees with Linux 6.1.7, commit 21e996306a6afaae88295858de0ffb8955173a15 . The following script has been used for the synchronization: $ for i in $(cd arch/arm/dts/ ; ls -1 r8a* | grep -v 'u-boot.dts' ; sed -n '/#include/ s@.*"\(.*\)"@\1@p' $(ls -1 r8a* | grep -v 'u-boot.dts')) ; do if [ -e /linux-2.6/arch/arm64/boot/dts/renesas/$i ] ; then cp /linux-2.6/arch/arm64/boot/dts/renesas/$i arch/arm/dts/ ; elif [ -e /linux-2.6/arch/arm/boot/dts/$i ] ; then cp /linux-2.6/arch/arm/boot/dts/$i arch/arm/dts/ else echo "NOT FOUND: $i" fi done $ git add $( ( cd arch/arm/dts/ ; ls -1 r8a* | grep -v 'u-boot.dts' ; sed -n '/#include/ s@.*"\(.*\)"@\1@p' $(ls -1 r8a* | grep -v 'u-boot.dts')) | tr " " "\n" | sed 's@^@arch/arm/dts/@g' ) Move the include/dt-bindings/{clk,clock}/versaclock.h header used by the renesas boards to match Linux 6.1.y as well. Keep arch/arm/dts/r8a774c0-u-boot.dtsi sdhi3 node as it is now used by the arch/arm/dts/r8a774c0-cat874.dts board. Pick s@spi-flash@flash@ change in arch/arm/dts/r8a779a0-falcon-u-boot.dts from "ARM: dts: Synchronize R-Car V3U DTs with Linux 5.18.3" . Adjust R8A77990 Ebisu CONFIG_SYS_MMC_ENV_DEV from 2 to 0 to reflect the card enumeration in ebisu.dtsi /aliases DT node . Adjust R8A7795 and R8A7796 ULCB CONFIG_SYS_MMC_ENV_DEV from 1 to 0 to reflect the card enumeration in ulcb.dtsi /aliases DT node . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> # r8a779a0-falcon-u-boot.dts Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> # r8a779a0-falcon-u-boot.dts
2023-01-27Merge tag 'xilinx-for-v2023.04-rc1' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx chnages for v2023.04-rc1 makefile: - Add multi_dtb_fit dependency clk: - Handle error cases microblaze: - Disable falcon mode and cleanup code around xilinx: - Enable regular expression matching in board_fit_config_name_match() - Fix FRU handling for 0xC1 format - Fix Xilinx legacy format eeprom parsing zynqmp: - Some DT updates/cleanups - Fix IDcode for xck24 - Remove empty mini config files - Add support for k24 versal: - Remove empty mini config files versal_net: - Setup timer when runs in EL3 - Build u-boot.elf for mini configurations zynq-gem: - Add support for new compatible strings - Remove support for Avnet Ultrazedev SOM - Handle SGMII with PCS phy spi: - Add support for gigadevice parts misc: - Remove CONFIG_TARGET_VENUS ifdef - Add missing headers to remove sparse warnings
2023-01-23clk: sunxi: Add DE2 display-related clocks/resetsSamuel Holland
Add clock/reset definitions for display-related peripherals, including the display engine, TCONs, and DSI and HDMI encoders, so those drivers can be converted to DM clock consumers instead of directly manipulating the CCU registers. Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-01-16clk: versal: Return error in case if clock setup failedJay Buddhabhatti
Currently probe is getting success even if clock setup is failed because of that u-boot is trying to access invalid clocks. So return error if clock setup failed. Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/fa78e71211e5f68f8dc1353b357f96e6283f65a8.1673335422.git.michal.simek@amd.com
2023-01-16clk: rockchip: Add rv1126 clk supportJagan Teki
Add clock driver support for Rockchip RV1126 SoC. Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16rockchip: clk: add watchdog clock to px30_clk_enableQuentin Schulz
Add the PCLK_WDT_NS clock to px30_clk_enable so that the watchdog driver can probe since it wants to enable this clock. Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-12-21Merge tag 'v2023.01-rc4' into nextTom Rini
Prepare v2023.01-rc4 Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-19rockchip: rk3128-cru: sync the clock dt-binding header from LinuxJohan Jonker
In order to update the DT for rk3128 sync the clock dt-binding header. This is the state as of v6.0 in Linux. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-12-09arm: mach-k3: am62a: introduce auto-generated SoC dataBryan Brattlof
Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
2022-12-07clk: stm32mp13: introduce STM32MP13 RCC driverGabriel Fernandez
STM32MP13 RCC driver uses Common Clock Framework and also a 'clk-stm32-core' API. Then STM32MPx RCC driver will contain only data configuration (gates, mux, dividers and the way to check security) or some specific clocks. This API will be used by all new other generations of ST Socs. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Tested-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-12-05global: Move remaining CONFIG_SYS_* to CFG_SYS_*Tom Rini
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-15clk: microchip: mpfs: fix criticality of peripheral clocksConor Dooley
Sync the critical clocks in the U-Boot driver with those marked as critical in Linux. The Linux driver has an explanation of why each clock is considered to be critical, so import that too. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
2022-11-15clk: microchip: mpfs: fix periph clk parentageConor Dooley
Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
2022-11-15clk: microchip: mpfs: fix reference clock handlingConor Dooley
The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
2022-11-15clk: microchip: mpfs: convert parent rate acquistion to get_get_rate()Conor Dooley
Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
2022-10-24Merge tag 'u-boot-imx-20221024' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20221024 ------------------- CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/13916 - for 2022.01 - rework Kontron boards (mx6 and mx8) - fixes for Toradex - fixes (SPI, CAAM, ) - sync DT with Linux - fixes for Gateworks GW7903 and GW7904 PMIC - Engicam i.Core MX8M Plus EDIMM2.2
2022-10-21clk-imx8mm: Only build QSPI clocks when CONFIG_NXP_FSPI=yFabio Estevam
The QSPI clocks are only used when CONFIG_NXP_FSPI=y, so only build the QSPI clocks in this case to reduce the final SPL binary size. Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-10-21clk-imx8mm: Only build ecspi clocks when CONFIG_DM_SPI=yFabio Estevam
The ecspi clocks are only used when CONFIG_DM_SPI=y, so only build the ecspi clocks in this case to reduce the final SPL binary size. Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-10-21clk-imx8mm: Move CLK_ENET_AXI to the non-SPL sectionFabio Estevam
Ethernet is not used inside SPL, so move the IMX8MM_CLK_ENET_AXI clock inside the non-SPL block to reduce the final SPL binary size. Signed-off-by: Fabio Estevam <festevam@denx.de>
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-15 16:04:07 +0000