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path: root/drivers/clk
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2021-01-18clk: Add Microchip PolarFire SoC clock driverPadmarao Begari
Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
2021-01-15dm: fix build errors generated by last mergesDario Binacchi
Something was wrong in the merge process into the mainline. Some added patches access driver structure fields and functions that have been modified by previous patches. The patch renames: - dev_get_platdata to dev_get_plat - dev_get_uclass_platdata to dev_get_uclass_plat - ofdata_to_platdata to of_to_plat - plat_data_alloc_size to plat_auto - priv_auto_alloc_size to priv_auto - video_uc_platdata to video_uc_plat Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-01-13Merge tag 'u-boot-stm32-20210113' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Enable logging features for stm32mp15 boards - Update MAINTAINERS emails for STI and STM32 - Activate OF_LIVE for ST stm32mp15 boards - Switch to MCO2 for PHY 50 MHz clock for DHCOM boards - Correction in stm32prog command on uart: always flush DFU on start command - Update USB-C power detection algorithm on DK boards
2021-01-13Merge tag 'u-boot-amlogic-20210112' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - sync amlogic GX & AXG DT to Linux 5.10 - Add new MESON_EE driver support for GXBB & AXG - Add support for Libretech-CC v2, Wetek Core2, Beelink GT-King/Pro boards - add driver for TDO tl070wsh30 panel driver - meson: isolate loading of socinfo - Add soc_rev to environment - Enable G12A support for saradc - Add correct mmcdev on VIM3(L) & Odroid-N2(C4) - Read MAC from fuses for VIM3 & VIM3L boards
2021-01-13clk: clk_stm32h7: migrate trace to dev and log macroPatrick Delaunay
Change debug and pr_ macro to dev macro and define LOG_CATEGORY. Remove the "%s:" __func__ header as it is managed by dev macro (dev->name is displayed) or log macro (CONFIG_LOGF_FUNC). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2021-01-13clk: clk_stm32f: migrate trace to dev and log macroPatrick Delaunay
Change debug and pr_ macro to dev macro and define LOG_CATEGORY. Remove the "%s:" __func__ header as it is managed by dev macro (dev->name is displayed) or log macro (CONFIG_LOGF_FUNC). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2021-01-13clk: stm32mp1: migrate trace to dev and log macroPatrick Delaunay
Change debug and pr_ macro to dev macro and define LOG_CATEGORY. Remove the "%s:" __func__ header as it is managed by dev macro (dev->name is displayed) or log macro (CONFIG_LOGF_FUNC). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2021-01-12clk: move clk-ti-sci driver to 'ti' directoryDario Binacchi
The patch moves the clk-ti-sci.c file to the 'ti' directory along with all the other TI's drivers, and renames it clk-sci.c. Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-01-12clk: ti: omap4: add clock manager driverDario Binacchi
This minimal driver is only used to bind child devices. For DT binding details see Linux doc: - Documentation/devicetree/bindings/arm/omap/prcm.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-01-12clk: ti: add support for clkctrl clocksDario Binacchi
Until now the clkctrl clocks have been enabled/disabled through platform routines. Thanks to this patch they can be enabled and configured directly by the probed devices that need to use them. For DT binding details see Linux doc: - Documentation/devicetree/bindings/clock/ti-clkctrl.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-01-12clk: ti: add gate clock driverDario Binacchi
The patch adds support for TI gate clock binding. The code is based on the drivers/clk/ti/gate.c driver of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/clock/ti/gate.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-01-12clk: ti: add divider clock driverDario Binacchi
The patch adds support for TI divider clock binding. The driver uses routines provided by the common clock framework (ccf). The code is based on the drivers/clk/ti/divider.c driver of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/clock/ti/divider.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-01-12clk: ti: am33xx: add DPLL clock driversDario Binacchi
The digital phase-locked loop (DPLL) provides all interface clocks and functional clocks to the processor of the AM33xx device. The AM33xx device integrates five different DPLLs: * Core DPLL * Per DPLL * LCD DPLL * DDR DPLL * MPU DPLL The patch adds support for the compatible strings: * "ti,am3-dpll-core-clock" * "ti,am3-dpll-no-gate-clock" * "ti,am3-dpll-no-gate-j-type-clock" * "ti,am3-dpll-x2-clock" The code is loosely based on the drivers/clk/ti/dpll.c drivers of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/clock/ti/dpll.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-01-12clk: ti: add mux clock driverDario Binacchi
The driver manages a register-mapped multiplexer with multiple input clock signals or parents, one of which can be selected as output. It uses routines provided by the common clock framework (ccf). The code is based on the drivers/clk/ti/mux.c driver of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/clock/ti/mux.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-01-12clk: add clk_round_rate()Dario Binacchi
It returns the rate which will be set if you ask clk_set_rate() to set that rate. It provides a way to query exactly what rate you'll get if you call clk_set_rate() with that same argument. So essentially, clk_round_rate() and clk_set_rate() are equivalent except the former does not modify the clock hardware in any way. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-01-12clk: export generic routinesDario Binacchi
Export routines that can be used by other drivers avoiding duplicating code. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-11clk: meson: add minimal driver for g12a-ao clocksMarek Szyprowski
Add minimal driver AO clocks on meson G12A family. Only ADC related clocks are supported. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-01-05Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into nextTom Rini
Driver model: make some udevice fields private Driver model: Rename U_BOOT_DEVICE et al. dtoc: Tidy up and add more tests ns16550 code clean-up x86 and sandbox minor fixes for of-platdata dtoc prepration for adding build-time instantiation
2021-01-05Merge tag 'v2021.01-rc5' into nextTom Rini
Prepare v2021.01-rc5 Signed-off-by: Tom Rini <trini@konsulko.com>
2021-01-05dm: Rename DM_GET_DRIVER() to DM_DRIVER_GET()Simon Glass
In the spirit of using the same base name for all of these related macros, rename this to have the operation at the end. This is not widely used so the impact is fairly small. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05dm: core: Access device ofnode through functionsSimon Glass
At present ofnode is present in the device even if it is never used. With of-platdata this field is not used, so can be removed. In preparation for this, change the access to go through inline functions. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05dm: core: Use dev_has_ofnode() instead of dev_of_valid()Simon Glass
We have two functions which do the same thing. Standardise on dev_has_ofnode() since there is no such thing as an 'invalid' ofnode in normal operation: it is either null or missing. Also move the functions into one place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2021-01-05dm: core: Access device flags through functionsSimon Glass
At present flags are stored as part of the device. In preparation for storing them separately, change the access to go through inline functions. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05dm: Use access methods for dev/uclass private dataSimon Glass
Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
2020-12-13dm: treewide: Rename ..._platdata variables to just ..._platSimon Glass
Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename ofdata_to_platdata() to of_to_plat()Simon Glass
This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename dev_get_platdata() to dev_get_plat()Simon Glass
Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass
We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: Remove uses of device_bind_offset()Simon Glass
This function is not needed since the standard device_bind() can be used instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: core: Rename device_bind() to device_bind_offset()Simon Glass
This function is not necessary anymore, since device_bind_ofnode() does the same thing and works with both flattree and livetree. Rename it to indicate that it is special. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-11Merge tag 'u-boot-atmel-fixes-2021.01-b' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-atmel Second set of u-boot-atmel fixes for 2021.01 cycle This set includes very important fixes for: MMC booting on several boards, drive strength on sam9x60ek mmc lines, compile issues for timer.c old driver, removal of unwanted access to sam9x60 bit for oscillator bypass mode, and eeproms read on sama5d2_icp.
2020-12-09Merge tag 'u-boot-stm32-20201209' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Manage CONFIG_ENV_EXT4_DEVICE_AND_PART in stm32mp1 board - Update ARM STI and ARM STM STM32MP Arch maintainers emails - Enable internal pull-ups for SDMMC1 on DHCOM SoM
2020-12-09treewide: Update email address Patrick Delaunay and Patrice ChotardPatrice Chotard
Update Patrick and my email address with the one dedicated to upstream activities. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-12-07clk: at91: sam9x60: remove the parsing of atmel, main-osc-bypassClaudiu Beznea
Remove the parsing of atmel,main-osc-bypass DT property as the SAM9X60 have no support for crystal oscillator bypass. Setting this bit might affect the device functionality. Fixes: a64862284f65 ("clk: at91: sam9x60: add support compatible with CCF") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-12-06imx: clk: added IPG Clock for I2C on imx8qmOliver Graute
This patch fixes this clk issue on I2C on imx8qm => i2c bus Bus 3: i2c@5a830000 => i2c dev 3 Setting bus to 3 Failed to enable ipg clk Failure changing bus number (-524) Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
2020-11-17clk: sunxi: add compatible string for V3Icenowy Zheng
A new compatible string is introduced for V3 CCU, because it has a few extra features available. Add the compatible string to the clock driver. As the extra features are not touched, just share the description struct now. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-11-13rockchip: rk3399: Init clocks in U-Boot proper if SPL was not runAlper Nebi Yasak
It's possible to chainload U-Boot proper from the vendor firmware in rk3399 chromebooks, but the way the vendor firmware sets up clocks is somehow different than what U-Boot expects. This causes the display to stay devoid of content even though vidconsole claims to work (with patches in process of being upstreamed). This is meant to be a rk3399 version of commit d3cb46aa8c41 ("rockchip: Init clocks again when chain-loading") which can detect the discrepancy, but this patch instead checks whether SPL (and therefore the clock init) was run via the handoff functionality and runs the init if it was not. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-10-30Merge tag 'u-boot-rockchip-20201031' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - New PX30 board: Engicam PX30.Core; - Fix USB HID support for rock960; - Remove host endianness dependency for rockchip mkimage; - dts update for rk3288-tinker; - Enable console MUX for some ROCKPi boards; - Add config-based ddr selection for px30;
2020-10-30clk: rockchip: rk3399: implement getting wdt/alive clocksJack Mitchell
In order to correctly calculate the designware watchdog timeouts, the watchdog clock is required. Implement required clocks to facilitate this. Signed-off-by: Jack Mitchell <ml@embed.me.uk> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-10-29dm: Use driver_info index instead of pointerSimon Glass
At present we use a 'node' pointer in the of-platadata phandle_n_arg structs. This is a pointer to the struct driver_info for a particular device, and we can use it to obtain the struct udevice pointer itself. Since we don't know the struct udevice pointer until it is allocated in memory, we have to fix up the phandle_n_arg.node at runtime. This is annoying since it requires that SPL's data is writable and adds a small amount of extra (generated) code in the dm_populate_phandle_data() function. Now that we can find a driver_info by its index, it is easier to put the index in the phandle_n_arg structures. Update dtoc to do this, add a new device_get_by_driver_info_idx() to look up a device by drive_info index and update the tests to match. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-29dm: test: Add a test for of-platdata phandlesSimon Glass
We have a test in dtoc for this feature, but not one in U-Boot itself. Add a simple test that checks that the information comes through correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-26clk: kendryte: no need to check argument of free()Heinrich Schuchardt
free() checks if its argument is NULL. No need to check it twice. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2020-10-22clk: ccf: replace the get_rate helperDario Binacchi
The 12d152620d commit fixed the get_rate helper because the set_parent one did not re-parent the clock device to the new parent. The 4d139f3838 commit allows you to remove this workaround by calling the clk_get_parent_rate routine. Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-10-20clk: renesas: Import R8A774C0 clock tables from Linux 5.9Lad Prabhakar
Import RZ/G2E (R8A774C0) clock tables from Linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20clk: renesas: Add R8A774E1 clock tablesBiju Das
This sync's the RZ/G2H clock tables with mainline linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20clk: renesas: Add R8A774B1 clock tablesBiju Das
This sync's the RZ/G2N clock tables with mainline linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20clk: renesas: r8a774a1-cpg-mssr: Add R8A774A1 RPC clockBiju Das
Add RPC entry into the R8A774A1 clock driver tables. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-19clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristicsEugen Hristev
This SoC has the 5th divisor for the mck0 master clock. Adapt the characteristics accordingly. Reported-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19clk: at91: clk-master: add 5th divisor for mck masterEugen Hristev
clk-master can have 5 divisors with a field width of 3 bits on some products. Change the mask and number of divisors accordingly. Reported-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-05 21:43:35 +0000