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path: root/drivers/ddr
AgeCommit message (Expand)Author
2016-05-02Fix spelling of "occurred".Vagrant Cascadian
2016-04-20ddr: altera: Repair DQ window centering codeMarek Vasut
2016-04-20ddr: altera: Staticize global variablesMarek Vasut
2016-04-20ddr: altera: Make DLEVEL behavior inclusiveMarek Vasut
2016-04-20ddr: altera: Zero DM IN delay in scc_mgr_zero_group()Marek Vasut
2016-04-20ddr: altera: Remove unnecessary ODT mode configMarek Vasut
2016-04-20ddr: altera: Remove unnecessary update of the SCCMarek Vasut
2016-04-20ddr: altera: Fix DRAM end value in protection ruleMarek Vasut
2016-04-20ddr: altera: Fix scc_mgr_set() argument orderMarek Vasut
2016-04-20ddr: altera: Tweak DQS tracking enable handlingMarek Vasut
2016-04-20ddr: altera: Replace ad-hoc constant with macroMarek Vasut
2016-03-27Fix typo choosen in comments and printf logsAlexander Merkle
2016-03-24arm: mvebu: Fix ddr3_init() cpu configDirk Eibach
2016-03-21driver/ddr/fsl: Add workaround for erratum A-009803Shengzhou Liu
2016-03-21driver/ddr/fsl: Add address parity support for DDR4 UDIMM/discreteShengzhou Liu
2016-02-06Use correct spelling of "U-Boot"Bin Meng
2016-02-01drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.Purna Chandra Mandal
2016-01-25drivers/ddr/fsl: fsl_ddr_sdram_size remove unused controllersEd Swarthout
2016-01-25driver/ddr/fsl: Add workaround for A009663Shengzhou Liu
2016-01-25fsl/ddr: Add workaround for ERRATUM_A009942Shengzhou Liu
2016-01-19Add more SPDX-License-Identifier tagsTom Rini
2016-01-16ddr: altera: Init the rule ID in debug codeMarek Vasut
2016-01-14mvebu: axp: Rename MV_DDR_32BIT to CONFIG_DDR_32BITPhil Sutter
2016-01-14axp: Fix debugging support in DDR3 write levelingPhil Sutter
2016-01-14arm: mvebu: Make ECC support configurable on Armada XPStefan Roese
2016-01-14arm: mvebu: ddr: Fix compilation warningStefan Roese
2015-12-15move erratum a008336 and a008514 to soc specific fileYao Yuan
2015-12-13fsl/ddr: updated ddr errata-A008378 for arm and power SoCsShengzhou Liu
2015-12-13driver/ddr/fsl: Update timing config for heavy loadYork Sun
2015-12-13driver/ddr/fsl: Update workaround for A008511 for vref rangeYork Sun
2015-12-13driver/ddr/fsl: Update MR5 RTT parkYork Sun
2015-12-13driver/ddr/fsl: Update DDR4 MR6 for Vref rangeYork Sun
2015-12-13driver/ddr/fsl: Update DDR4 RTT valuesYork Sun
2015-11-30drivers/ddr/fsl: Fix typo in BIST test for DDR4York Sun
2015-11-30drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3York Sun
2015-11-30armv8: ls2085a: Add support of LS2085A SoCPrabhakar Kushwaha
2015-11-30armv8: LS2080A: Rename LS2085A to reflect LS2080APrabhakar Kushwaha
2015-11-17arm: mvebu: Fix SAR1_CPU_CORE_MASKDirk Eibach
2015-11-17arm: mvebu: a38x: Remove unsupported topologiesKevin Smith
2015-11-10Various Makefiles: Add SPDX-License-Identifier tagsTom Rini
2015-10-30drivers/ddr/fsl_ddr: Make SR_IE configurableJoakim Tjernlund
2015-09-11bitops: introduce BIT() definitionHeiko Schocher
2015-08-23ddr: altera: Repair uninited variableMarek Vasut
2015-08-23ddr: altera: Replace float multiplication with integer oneMarek Vasut
2015-08-17arm: mvebu: Add complete SDRAM ECC scrubbingStefan Roese
2015-08-17arm: mvebu: sdram: Enable ECC support on Armada XPStefan Roese
2015-08-08ddr: altera: sequencer: Clean checkpatch issuesMarek Vasut
2015-08-08ddr: altera: sequencer: Clean data typesMarek Vasut
2015-08-08ddr: altera: sequencer: Pluck out misc macros from codeMarek Vasut
2015-08-08ddr: altera: sequencer: Zap SEQ_T(INIT|RESET)_CNTR._VALMarek Vasut