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path: root/drivers/gpio
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2023-11-02gpio: rzg2l: Drop <common.h>Paul Barker
In line with changes elsewhere, drop inclusion of the common header. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2023-10-22pinctrl: sunxi: add new D1 pinctrl supportAndre Przywara
For the first time since at least the Allwinner A10 SoCs, the D1 (and related cores) use a new pincontroller MMIO register layout, so we cannot use our hardcoded, fixed offsets anymore. Ideally this would all be handled by devicetree and DM drivers, but for the DT-less SPL we still need the legacy interfaces. Add a new Kconfig symbol to differenciate between the two generations of pincontrollers, and just use that to just switch some basic symbols. The rest is already abstracted enough, so works out of the box. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Sam Edwards <CFSworks@gmail.com> Tested-by: Sam Edwards <CFSworks@gmail.com> Tested-by: Samuel Holland <samuel@sholland.org>
2023-10-22pinctrl: sunxi: remove GPIO_EXTRA_HEADERAndre Przywara
U-Boot's generic GPIO_EXTRA_HEADER is a convenience symbol to allow code to more easily include platform specific GPIO headers. This should not be needed in a DM world anymore, since the generic GPIO framework handles that nicely. For Allwinner boards we still need to deal with non-DM GPIO in the SPL, but this should become the exception, not the rule. Make this more obvious by removing the definition of GPIO_EXTRA_HEADER, and just force every legacy user of platform specific GPIO to include the new sunxi_gpio.h header explicitly. Everyone doing so should feel ashamed and should find a way to avoid it from now on. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Samuel Holland <samuel@sholland.org>
2023-10-22pinctrl: sunxi: remove struct sunxi_gpioAndre Przywara
So far every Allwinner SoC used the same basic pincontroller/GPIO register frame, and just differed by the number of implemented banks and pins, plus some special functionality from time to time. However the D1 and successors use a slightly different pinctrl register layout. Use that opportunity to drop "struct sunxi_gpio", that described that MMIO frame in a C struct. That approach is somewhat frowned upon in the Linux world and rarely used there, though still popular with U-Boot. Switching from a C struct to a "base address plus offset" approach allows to switch between the two models more dynamically, without reverting to preprocessor macros and #ifdef's. Model the pinctrl MMIO register frame in the usual "base address + offset" way, and replace a hard-to-parse CPP macro with a more readable static function. All the users get converted over. There are no functional changes at this point, it just prepares the stages for the D1 and friends. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Tested-by: Samuel Holland <samuel@sholland.org>
2023-10-22pinctrl: sunxi: add GPIO in/out wrappersAndre Przywara
So far we were open-coding the pincontroller's GPIO output/input access in each function using that. Provide functions that wrap that nicely, and follow the existing pattern (set/get_{bank,}), so users don't need to know about the internals, and we can abstract the new D1 pinctrl more easily. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org>
2023-10-22pinctrl: sunxi: move pinctrl codeAndre Przywara
Move the existing sunxi-specific low level pinctrl routines from arch/arm/mach-sunxi into the existing GPIO code under drivers/gpio, so that the common code can be shared outside of arch/arm. This also takes the opportunity to move some definitions from our header file into the driver C file, as they are private to the driver and are not needed elsewhere. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Tested-by: Samuel Holland <samuel@sholland.org>
2023-10-16gpio: Add RZ/G2L GPIO driverPaul Barker
This driver adds support for the gpio features of the GPIO/PFC module in the Renesas RZ/G2L (R9A07G044) SoC. The new `rzg2l-pfc-gpio` driver is bound to the same device tree node as the `rzg2l-pfc-pinctrl` driver as the same hardware block provides both GPIO and pin multiplexing features. This patch is based on the corresponding Linux v6.5 driver (commit 52e12027d50affbf60c6c9c64db8017391b0c22e). Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-13treewide: use dev_read_addr_*_ptr() where appropriateMatthias Schiffer
A follow-up to commit 842fb5de424e ("drivers: use devfdt_get_addr_size_index_ptr when cast to pointer") and commit 320a1938b6f7 ("drivers: use devfdt_get_addr_index_ptr when cast to pointer"). In addition to using the *_ptr variants of these functions where the address is cast to a pointer, this also changes devfdt_get_addr_*() to dev_read_addr_*() in a few places. Some variable and field types are changed from fdt_addr_t or phys_addr_t to void* where the cast was happening later. This patch fixes a number of compile warnings when building a 32bit U-Boot with CONFIG_PHYS_64BIT=y. In some places, it also fixes error handling where the return value of dev_read_addr() etc. was checked for NULL instead of FDT_ADDR_T_NONE. Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-09-14gpio: Remove unused NEEDS_MANUAL_RELOC code bitsMarek Vasut
The last user of the NEEDS_MANUAL_RELOC has been removed in commit 26af162ac8f8 ("arch: m68k: Implement relocation") Remove now unused NEEDS_MANUAL_RELOC code. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-08-17gpio: pca953x: Add TI TCA9554 supportMarek Vasut
Add support for TI TCA9554, which is compatible with PCA9554 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-08-14gpio: Use separate bitfield array to indicate GPIO is claimedMarek Vasut
The current gpio-uclass design uses name field in struct gpio_dev_priv as an indicator that GPIO is claimed by consumer. This overloads the function of name field and does not work well for named pins not configured as GPIO pins. Introduce separate bitfield array as the claim indicator. This unbreaks dual-purpose AF and GPIO operation on STM32MP since commit 2c38f7c31806 ("pinctrl: pinctrl_stm32: Populate uc_priv->name[] with pinmux node's name") where any pin which has already been configured as AF could no longer be claimed as dual-purpose GPIO. This is important for pins like STM32 MMCI st,cmd-gpios . Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-07-17x86: Convert some debug statements to use loggingSimon Glass
Move from using debug() to log_debug() so that we don't have to use the __func__ parameter and can access other logging features. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-14gpio: Avoid using an invalid ofnodeSimon Glass
Devices do not necessarily have nodes attached to them, since they can be created from platdata. In SPL a devicetree may in fact not exist at all. Check the node before using it. This avoids failure when OF_CHECKS is enabled. Signed-off-by: Simon Glass <sjg@chromium.org> Fixes: 5fc7cf8c8e2 ("gpio: add gpio-hog support") Reviewed-by: Heiko Schocher <hs@denx.de>
2023-06-12Merge tag 'xilinx-for-v2023.10-rc1' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2023.10-rc1 global: - Use proper U-Boot project name Fix sparse warnings in zynqmp-clk, zynqmp handoff, board cmd: - Cover incorrect 0 length entries Versal NET: - Add bootmode logic - Support SPP production version - Add loadpdi command ZynqMP: - Clear pmufw node command ID handling - Change power domain behavior around zynqmp_pmufw_node() - Fix zynqmp cmd return values and pmufw command - Fix R5 tcm init and modes mmc: - Sync Versal NET emmc DT binding pcie: - Add support for ZynqMP PCIe root port video: - Add support for ZynqMP DP tools: - Fix debug message in relocate-rela
2023-06-12Merge tag v2023.07-rc4 into nextTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-06-12global: Use proper project name U-BootMichal Simek
Use proper project name in comments, Kconfig, readmes. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Qu Wenruo <wqu@suse.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/0dbdf0432405c1c38ffca55703b6737a48219e79.1684307818.git.michal.simek@amd.com
2023-06-01pinctrl: nuvoton: set output state before enabling the outputJim Liu
The default output state may be different to request, change the configuration sequence to avoid glitch. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2023-05-16gpio: renesas: Simplify .request/.rfree callbacksPali Rohár
Remove identify wrapper functions. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Marek Vasut <marex@denx.de>
2023-05-06drivers: use dev_read_addr_ptr when cast to pointerJohan Jonker
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use dev_read_addr_ptr instead of the dev_read_addr function in the various files in the drivers directory that cast to a pointer. As we are there also streamline the error response to -EINVAL on return. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-30Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini
Please pull the second part of the sunxi pull request for this cycle. Another bunch of patches that replace old-school U-Boot hacks with proper DM based code, this time for the raw NAND flash driver, and the USB PHY VBUS detection code. Plus two smaller patches that were sitting in my inbox for a while. Gitlab CI passed. In lack of some supported board with NAND flash I couldn't really test this part, but apparently this was tested by the reviewer. I briefly ran the branch on some boards with USB-OTG, and this still worked.
2023-04-29Merge branch 'for-2023.07' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-mpc8xx This pull request adds support for the last CPU board from CS GROUP France (previously CSSI). That CPU board called CMPCPRO has a mpc8321E CPU (Family PQII PRO hence its name) and can be plugged in place of the CMPC885 board. In order to support that new board, the following changes are included in this series: - Make the mpc8xx watchdog driver more generic for reusing it with mpc83xx - Fix various small problems on mpc83xx platform - Add a GPIO Driver for QE GPIOs - Add support for mpc832x into mpc83xx SPI driver - Refactor existing board code that will be shared with new board - Add the new board
2023-04-28gpio: axp/sunxi: Remove virtual VBUS detection GPIOSamuel Holland
Now that this functionality is modeled using the device tree and regulator uclass, the named GPIO is not referenced anywhere. Remove it. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-25gpio-uclass: fix off-by-one in gpio_request_list_by_name_nodev()Rasmus Villemoes
By the time we jump to the err label, count represents the number of gpios we've successfully requested. So by subtracting one, we fail to free the most recently requested. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-21gpio: rockchip: Add support for RK3568 and RK3588 banksJonas Karlman
The GPIO V2 controller on RK3568 and RK3588 works very similar to prior generation, main difference is the use of a write mask in the upper 16 bits and register address offset have changed. GPIO_VER_ID is a new register at 0x0078 that is used to determine when the driver should use new or old register offsets and values. Earlier generation return 0x0 from this offset. Refactor code and add support for the GPIO V2 controller used in RK3568 and RK3588. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21rockchip: gpio: rk_gpio: use ROCKCHIP_GPIOS_PER_BANK as dividerJohan Jonker
The current divider to calculate the bank ID can change. Given the Rockchip TRM not all gpio-banks have 32 pins per bank. The "gpio-ranges" syntax allows multiple items with variable number of pins. Use a constant ROCKCHIP_GPIOS_PER_BANK as fixed divider. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-07pinctrl: renesas: Add R8A779F0 S4 PFC tablesLUU HOAI
Add pinctrl tables for R8A779F0 S4 SoC. Based on Linux next 20230228 PFC tables tables up to commit 058f4df42121 ("Add linux-next specific files for 20230228") Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Use RCAR_64 Kconfig, sync with Linux next 20230228]
2023-04-07gpio: renesas: Add R-Car Gen4 supportHai Pham
Add support for the GPIO controller block in the R-Car Gen4 family. It has a General Input Enable Register (INEN), whose reset state is to have all inputs disabled. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-04-06gpio: Add QUICC Engine GPIOs driverChristophe Leroy
The mpc832x has GPIOs handled by the QUICC Engine. The registers are different from the one for the non QE mpc83xx GPIOs. Implement a GPIO driver for those. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2023-03-30gpio: allow passing NULL to gpio_request_by_line_name() to search all gpio ↵Rasmus Villemoes
controllers The API is more convenient to use if one doesn't have to know upfront which gpio controller has a line with the name one is searching for, and arrange to look that device up somehow. Or implement this loop oneself. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-18pinctrl: renesas: Replace ifdeffery with IS_ENABLED()Marek Vasut
Switch ifdef in sh_gpio_get_value() to IS_ENABLED() macro. The CONFIG_RCAR_GEN3 will never have SPL counterpart, so the IS_ENABLED() macro is the right one here. No functional change, except for improved build test coverage. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-28gpio: gpio-rockchip: parse gpio-ranges for bank idChris Morgan
Use the new devicetree property of gpio-ranges to determine the GPIO bank ID. Preserve the "old" way of doing things too, so that boards can be migrated and tested gradually (I only have a 3566 and 3326 to test). Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-12Merge branch 'for-2023.04' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-mpc8xx - A fix for a long standing bug that has been exposed by commit 50128aeb0f8 ("cyclic: get rid of cyclic_init()") preventing 8xx boards from booting since u-boot 2023.01 - A GPIO driver for powerpc 8xx chip - Fixup for powerpc 8xx SPI driver - A new powerpc 8xx board - The two devices having that board.
2023-02-11driver, gpio: Add support for MPC 8xx CPU portsChristophe Leroy
Ports A, C and D are 16 bits ports. Ports B and E are 32 bits ports. The "compatible" is used to determine each port type. This patch was originally written by Charles Frey who's email address is not valid anymore as he left the company. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Reviewed-by: FRANJOU Stephane <stephane.franjou@csgroup.eu>
2023-02-10gpio: qcom: add direction functions for pwrkeyDzmitry Sankouski
GPIO button driver requires direction functions to probe button gpio. Those functions are blank, since pwrkey is not really gpio, and don't support direction settings. Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
2023-02-07gpio: Drop unused pca9698 driverSimon Glass
This is not used. Drop the driver and Kconfig option. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-07gpio: Drop unused mpc83xx_gpio driverSimon Glass
This is not used since this commit: 7458f18e5c2 ppc: Remove MPC8313ERDB boards Drop the driver and Kconfig option. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-07arm: Drop old kona codeSimon Glass
The KONA and KONA_GPIO options don't exist anymore, since this commit: 0f6807e77b0 arm: Remove bcm28155_ap board Drop the dead code. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-07Drop CONFIG_DM644X_GPIOSimon Glass
Drop this unused option. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-07gpio: Drop adi_gpio2Simon Glass
Drop this unused driver. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-02pinctrl: renesas: Synchronize PFC core with Linux 6.1.7Marek Vasut
Synchronize R-Car PFC core with Linux 6.1.7, commit 21e996306a6afaae88295858de0ffb8955173a15 . Parts picked from pinctrl: renesas: Synchronize R-Car Gen2/Gen3 tables with Linux 5.18.3 - Add pin groups for the green and high8 subsets of the Video IN pins - Add MediaLB pins - Add bias support for various SoCs - Share more pin group data, to reduce size and ease review - Miscellaneous cleanups, fixes and improvements. This contains port of Linux kernel commit 6210905586ae ("pinctrl: renesas: Add shorthand for reserved register fields") to handle negative entries in GROUP() macros correctly. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-01-27Merge tag 'xilinx-for-v2023.04-rc1' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx chnages for v2023.04-rc1 makefile: - Add multi_dtb_fit dependency clk: - Handle error cases microblaze: - Disable falcon mode and cleanup code around xilinx: - Enable regular expression matching in board_fit_config_name_match() - Fix FRU handling for 0xC1 format - Fix Xilinx legacy format eeprom parsing zynqmp: - Some DT updates/cleanups - Fix IDcode for xck24 - Remove empty mini config files - Add support for k24 versal: - Remove empty mini config files versal_net: - Setup timer when runs in EL3 - Build u-boot.elf for mini configurations zynq-gem: - Add support for new compatible strings - Remove support for Avnet Ultrazedev SOM - Handle SGMII with PCS phy spi: - Add support for gigadevice parts misc: - Remove CONFIG_TARGET_VENUS ifdef - Add missing headers to remove sparse warnings
2023-01-27gpio: zynqmp: Handle error from get_gpio_modepinAlgapally Santosh Sagar
There is a unused variable ret, due to which we are getting sparse warning as below. warning: variable 'ret' set but not used [-Wunused-but-set-variable]. Return ret incase of error. Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230120053617.32463-3-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-01-20global: Finish CONFIG -> CFG migrationTom Rini
At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-12gpio: Get rid of gpio_hog_probe_all()Marek Vasut
The gpio_hog_probe_all() functionality can be perfectly well replaced by DM_FLAG_PROBE_AFTER_BIND DM flag, which would trigger .probe() callback of each GPIO hog driver instance after .bind() and thus configure the hogged GPIO accordingly. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Samuel Holland <samuel@sholland.org>
2022-12-05Convert CONFIG_SH_GPIO_PFC et al to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SH_GPIO_PFC CONFIG_TMU_TIMER Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05Convert CONFIG_PCA953X to KconfigTom Rini
This converts the following to Kconfig: CONFIG_PCA953X Cc: Uri Mashiach <uri.mashiach@compulab.co.il> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05arm: Remove unused mx27 codeTom Rini
We no longer have any i.MX27 platforms, remove the remaining support code. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05Convert CONFIG_HIKEY_GPIO et al to KconfigTom Rini
This converts the following to Kconfig: CONFIG_HIKEY_GPIO CONFIG_TCA642X Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05global: Move remaining CONFIG_SYS_* to CFG_SYS_*Tom Rini
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-31arm: bcmbca: replace ARCH_BCM6753 symbols in Kconfig with BCM6855William Zhang
As CONFIG_ARCH_BCM6753 is replaced with CONFIG_BCM6855, update the driver Kconfig to use the new config symbol. Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
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