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2018-04-16Merge git://git.denx.de/u-boot-x86Tom Rini
2018-04-16pci: video: Only print out when everything is OKBin Meng
If video initialization fails, the "Video:" output message will be mixed with the next console log. Change to print out such message only when everything is OK, which improves the boot log readability. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-04-16video: vesa: Change default FRAMEBUFFER_VESA_MODEBin Meng
This changes the default FRAMEBUFFER_VESA_MODE to use 32-bit pixel format for better VxWorks compatibility. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-04-16bios: vesa: Guard setting vesa mode with CONFIG_FRAMEBUFFER_SET_VESA_MODEBin Meng
If CONFIG_FRAMEBUFFER_SET_VESA_MODE is not set, don't switch graphics card to VESA mode. This applies to both native mode and emulator mode of running the VGA BIOS. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-04-16mtd: cfi_flash: Make live-tree compatibleMario Six
Make the cfi_flash driver compatible with a live device tree. Signed-off-by: Mario Six <mario.six@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de>
2018-04-15Merge git://git.denx.de/u-boot-imxTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-15Merge git://git.denx.de/u-boot-netTom Rini
2018-04-15imx31_phycore: DeleteTom Rini
This platform has been marked as orphaned since September 2013, remove. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-14mmc: tmio: Rename Matsushita to TMIOMarek Vasut
Synchronize the naming with Linux, call the common code TMIO. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-13serial: sh: Add SCIFA0 address entryMarek Vasut
Add the SCIFA0 address entry so it can be used in TPL if needed due to size restrictions. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-13net: sh_eth: Add remaining Gen2 DT compatibleMarek Vasut
Add compatible strings for R8A7790, R8A7793 and R8A7794, since the contemporary DTs use those don't have a generic match value. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-04-13clk: renesas: Minor clean up of the R8A7790 clock driverMarek Vasut
The initconst is not used in U-Boot, drop it. The r8a7790_crit_mod_clks is also not used in U-Boot, so drop it too. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-13net: phy: Don't limit phy addresses by defaultJoe Hershberger
Some boards expect to find more than one phy while other boards are old and need to be limited to a specific phy address. Only limit the phy address for boards that opt in. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-13net: sh_eth: Add remaining Gen2 DT compatibleMarek Vasut
Add compatible strings for R8A7790, R8A7793 and R8A7794, since the contemporary DTs use those don't have a generic match value. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-04-13net: zynq_gem: Use max-speed property from dtSiva Durga Prasad Paladugu
Add support to use max-speed property from dt for determining the supported speed. Use 1000Mbps as default. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-04-13net: fec: Fix issue in DM probe timeoutYe Li
Since the probe function has changed to reset FEC controller prior than setup PHY. If reset FEC controller timeout, the priv->phydev is not initialized, so can't free it. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-04-13net: fex_mxc: add i.MX6UL/SX/SL compatiblePeng Fan
Add i.MX6UL/SX/SL compatible. Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-04-13net: fec: sharing MDIO for two enet controllersPeng Fan
On i.MX6SX, 6UL and 7D, there are two enet controllers each has a MDIO port. But Some boards share one MDIO port for the two enets. So introduce a configuration CONFIG_FEC_MXC_MDIO_BASE to indicate the MDIO port for sharing. In Kconfig, user needs enable CONFIG_FEC_MXC_SHARE_MDIO first to enter the CONFIG_FEC_MXC_MDIO_BASE. To i.MX28, adapt to use the new config Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Fabio Estevam <fabio.estevam@nxp.com>
2018-04-13net: fec: set dev->seq to priv->dev_idPeng Fan
To platforms has two enet interface, using dev->seq could avoid conflict. i.MX6UL/ULL evk board net get the wrong MAC address from fuse, eth1 get MAC0 address, eth0 get MAC1 address from fuse. Set the priv->dev_id to device->seq as the real net interface alias id then .fec_get_hwaddr() read the related MAC address from fuse. Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-04-13net: fec_mxc: simplify fec_get_miibusPeng Fan
No need to provide two prototype for this function. Use ulong for the first parameter, then this function could be shared for DM/non DM case. Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-04-13net: fec_mxc: Fix DM driver issue in recvYe Li
When using ethernet DM driver, the recv interface has a change with non-DM interface, that driver needs to set the packet pointer and provide it to upper layer to process. In fec driver, the fecmxc_recv functions does not handle the packet pointer parameter. This may cause crash in upper layer processing because the packet pointer is not set. This patch allocates a buffer for the packet pointer and free it through free_pkt interface. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-04-13net: mvneta: support setting hardware addressMatt Pelland
mvneta already supports setting the MAC address but this was only done internally when some other part of U-Boot tries to actually use the interface. This commit exposes this functionality to the ethernet core code so that the MAC addresses of all interfaces are configured correctly even if they are not used before loading Linux. Signed-off-by: Matt Pelland <mpelland@starry.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-04-13dwc_ahci: Fix breakageJean-Jacques Hiblot
The dwc_ahci has been broken for quite some time now. The breakage has been introduced by the series "dm: scsi: Enhance SCSI support for driver model" Use ahci_bind_scsi() and ahci_probe_scsi() to properly bind and probe the driver. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-04-13Merge git://git.denx.de/u-boot-shTom Rini
2018-04-13Merge git://git.denx.de/u-boot-usbTom Rini
2018-04-11spi: sh_qspi: Make use of the 32byte FIFOMarek Vasut
The QSPI controller on RCar Gen2 has 32byte FIFO. Instead of doing the SPI transmission 1 byte at time, if there is a 32byte chunk of data to be transferred, fill the FIFO completely and then transfer the data to/from the FIFO. This increases the SPI NOR access speed significantly. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2018-04-11spi: sh_qspi: Replace ad hoc waiting with wait_for_bitMarek Vasut
Replace the ad-hoc endless loops with wait_for_bit() with reasonable timeout. Note that the loops had internal 10uS delays, although there is no reason for those on this HW, so they are dropped. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2018-04-11spi: sh_qspi: Drop SPBDCR waitMarek Vasut
Waiting for SPBDCR == 1 is not required and is covered by the subsequent wait for SPSR_SPRFF, so drop this. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2018-04-11spi: sh_qspi: Replace data types with short onesMarek Vasut
Just replace unsigned {char,short,long} with u{8,16,32}, no functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2018-04-11mtd: spi: Add Renesas RPC SPI-flash driverMarek Vasut
Add driver for the RPC block in SPI-flash mode. This driver allows access to a SPI NOR flash attached to the RPC block and does not support RPC in Hyperflash mode. Note that this block is extremely selective when communicating with the SPI NOR. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-11mtd: rpc: Add Renesas RPC Hyperflash driverMarek Vasut
Add driver for the RPC block in Hyperflash mode. This driver allows access to a CFI Hyperflash attached to the RPC block and does not support RPC in SPI mode. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-11mmc: renesas-sdhi: Wait after reconfiguring pinsMarek Vasut
The IP requires some time to recuperate after the IO pin properties were changed. Add a delay to assure this. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: matsushita-common: Add missing elseMarek Vasut
Fix minor rebase omission, the else was missing which triggered two accesses to the register on 64bit variant of the IP. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: matsushita-common: Wait for command completionMarek Vasut
Make sure to wait for the command to complete altogether, including the trailing 8 clock cycles. This prevents the driver for accidentally writing the CMD register too fast before the previous command fully completed. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: matsushita-common: Correctly set mode in 16bitMarek Vasut
The HOST_MODE register must be set to 0 when the IP is operated in 16bit mode, otherwise 16bit access to the data FIFO may fail. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: matsushita-common: Special case only select registers in 16bitMarek Vasut
There are only a few registerse used in the 16bit mode which are 32bit internally. Special-case only those in the IO accessors and always write both halves. Any other register access is protected from accidentally overwriting neighboring register. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: renesas-sdhi: Add Renesas SDR104/HS200 tuning supportMarek Vasut
Add code for PHY tuning required for SDR104/HS200 support on Renesas RCar. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: matsushita-common: Export register access functionsMarek Vasut
Export the matsu_sd_{read,write}l() common register access functions, so that they can be used by other drivers sharing the common code. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: matsushita-common: Properly handle pin voltage configurationMarek Vasut
Factor out the regulator handling into set_ios and add support for selecting pin configuration based on the voltage to support UHS modes. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: matsushita-common: Always check controller versionMarek Vasut
Handle the controller version even if quirks are set. The controller in Renesas Gen3 SoCs does provide the version register, which indicates a controller v10 and the controller does support internal DMA and /1024 divider. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: matsushita-common: Handle bus width 0Marek Vasut
Handle bus width 0 as 1-bit bus to assure valid content of MATSU_SD_OPTION register WIDTH field. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: matsushita-common: Handle DMA completion flag differencesMarek Vasut
The DMA READ completion flag position differs on Socionext and Renesas SoCs. It is bit 20 on Socionext SoCs and using bit 17 is a hardware bug and forbidden. It is bit 17 on Renesas SoCs and bit 20 does not work on them. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: matsushita-common: Handle Renesas div-by-1Marek Vasut
On the Renesas version of the IP, the /1 divider is realized by setting the clock register [7:0] to 0xff instead of setting bit 10 of the register. Check the quirk and handle accordingly. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: matsushita-common: Add Renesas RCar quirksMarek Vasut
Add a quirk to identify that the controller is Renesas RCar variant of the Matsushita SD IP and another quirk indicating it can support Renesas RCar HS200/HS400/SDR104 modes. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: matsushita-common: Use mmc_of_parse()Marek Vasut
Drop the ad-hoc DT caps parsing in favor of common framework function. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: renesas-sdhi: Handle 16bit IPMarek Vasut
The Renesas RCar Gen2 chips have a mix of 32bit and 16bit variants of the IP. There is no DT property which allows discerning those, so what Linux does is it checks the size of the register area and if it is 0x100, the IP is 16bit, otherwise the IP is 32bit. Handle the distinction the same way. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: uniphier: Allow passing quirks to the probe functionMarek Vasut
Certain instances of the SD IP require more elaborate digging in the DT to figure out which variant of the SD IP is in use. Allow explicit passing of the quirks into the probe function. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: uniphier: Add support for 16bit variantMarek Vasut
Add support for 16bit mutation of the Matsushita SD IP. Since some registers are internally 32bit, the matsu_sd_{read,write}l() has to special-case this 16bit variant a bit. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: uniphier: Drop useless checkMarek Vasut
Drop useless check in matsu_sd_{read,write}q(), this is only ever called to read the data from FIFO and only when 64bit variant of the block is used anyway. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: uniphier: Factor out FIFO accessorsMarek Vasut
Add macros to generate the FIFO accessors, since the code is almost the same with only minor differences. This is done in preparation for adding 16bit variant of the IP. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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