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2023-06-21usb: dwc2: Fix the write to W1C fields in HPRT registerTeik Heng Chong
Fix the write to the HPRT register which treat W1C fields as if they were mere RW. This leads to unintended clearing of such fields This bug was found during the testing on Simics model. Referring to specification DesignWare Cores USB 2.0 Hi-Speed On-The-Go (OTG) Databook (3.30a)"5.3.4.8 Host Port Control and Status Register (HPRT)", the HPRT.PrtPwr is cleared by this mistake. In the Linux driver (contrary to U-Boot), HPRT is always read using dwc2_read_hprt0 helper function which clears W1C bits. So after write back those bits are zeroes. Signed-off-by: Teik Heng Chong <teik.heng.chong@intel.com>
2023-06-14net: rtl8169: add depends on PCIEugen Hristev
The rtl8169 driver uses calls to dm_pci_bus_to_phys, which are compiled under CONFIG_PCI. Without CONFIG_PCI, this happens: drivers/net/rtl8169.o: in function `rtl_recv_common': drivers/net/rtl8169.c:555: undefined reference to `dm_pci_bus_to_phys' It is only natural that this driver depends on CONFIG_PCI then. The device does not work connected in another way anyway, and the driver does not assume anything else at this moment. Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-06-08Merge https://source.denx.de/u-boot/custodians/u-boot-usbTom Rini
2023-06-08pinctrl: renesas: r8a779a0: Remove incorrect AVB[01] pinmux configurationHai Pham
AVB[01]_{MAGIC,MDC,MDIO,TXCREFCLK} are registered as both PINMUX_SINGLE(fn) and PINMUX_IPSR_GPSR(fn) in the pinmux_data array. The latter are correct, hence remove the former. Without this fix, the Ethernet PHY is not operational on the MDIO bus. Ported from Linux kernel commit a145c9a8674ac8fbfa1595276e1b6cbfc5139038 . Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com> Fixes: 741a7370fc3b8b54 ("pinctrl: renesas: Initial R8A779A0 (V3U) PFC support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/6fd217b71e83ba9a8157513ed671a1fa218b23b6.1674824958.git.geert+renesas@glider.be --- Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Hai Pham <hai.pham.ud@renesas.com> Cc: LUU HOAI <hoai.luu.ub@renesas.com> Cc: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-06-08usb: musb-new: sunxi: remove unused defineSam Edwards
This is a remnant from when the USB controller driver managed the reset signal itself. A patch from the very end of 2018 changed this driver to delegate reset (and clock) management to the proper control unit driver, but left this unused define behind. Signed-off-by: Sam Edwards <CFSworks@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de>
2023-06-07phy: rockchip-inno-usb2: Implement clock operations for usb2phy clockXavier Drudis Ferran
This clock doesn't seem needed but appears in a phandle list used by ehci-generic.c to bulk enable it. The phandle list comes from linux, where it is needed for suspend/resume to work [1]. My tests give the same results with or without this patch, but Marek Vasut found it weird to declare an empty clk_ops [2]. So I adapted the code from linux 6.1-rc8 so that it hopefully works if it ever has some user. For now, without real use, it seems to at least not give any errors when called. Link: [1] https://lkml.kernel.org/lkml/1731551.Q6cHK6n5ZM@phil/T/ [2] https://patchwork.ozlabs.org/project/uboot/patch/Y5IWpjYLB4aXMy9o@localhost/ Cc: Simon Glass <sjg@chromium.org> Cc: Philipp Tomsich <philipp.tomsich@vrull.eu> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Lukasz Majewski <lukma@denx.de> Cc: Sean Anderson <seanga2@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Christoph Fritz <chf.fritz@googlemail.com> Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Xavier Drudis Ferran <xdrudis@tinet.cat> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # rk3399, rk3328, rv1126
2023-06-07phy: rockchip-inno-usb2: Add usb2phy clock provider of 480MHz clockXavier Drudis Ferran
arch/arm/dts/rk3399.dtsi has a node usb_host0_ehci: usb@fe380000 { compatible = "generic-ehci"; with clocks: clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, <&u2phy0>; The first 2 refer to nodes with class UCLASS_CLK, but &u2phy0 has class UCLASS_PHY. u2phy0: usb2phy@e450 { compatible = "rockchip,rk3399-usb2phy"; Since clk_get_bulk() only looks for devices with UCLASS_CLK, it fails with -ENODEV and then ehci_usb_probe() aborts. The consequence is peripherals connected to a USB 2 port (e.g. in a Rock Pi 4 the white port, nearer the edge) not being detected. They're detected if CONFIG_USB_OHCI_GENERIC is selected in Kconfig, because ohci_usb_probe() does not abort when one clk_get_by_index() fails, but then they work in USB 1 mode. rk3399.dtsi comes from linux and the u2phy0 was added[1] to the clock list in: commit b5d1c57299734f5b54035ef2e61706b83041f20c Author: William wu <wulf@rock-chips.com> Date: Wed Dec 21 18:41:05 2016 +0800 arm64: dts: rockchip: add u2phy clock for ehci and ohci of rk3399 We found that the suspend process was blocked when it run into ehci/ohci module due to clk-480m of usb2-phy was disabled. [...] Suspend concerns don't apply to U-Boot, and the problem with U-Boot failing to probe EHCI doesn't apply to linux, because in linux rockchip_usb2phy_clk480m_register makes u2phy0 a proper clock provider when called by rockchip_usb2phy_probe(). So I can think of a few alternative solutions: 1- Change ehci_usb_probe() to make it more similar to ohci_usb_probe(), and survive failure to get one clock. Looks a little harder, and I don't know whether it could break something if it ignored a clock that was important for something else than suspend. 2- Change rk3399.dtsi effectively reverting the linux commit b5d1c57299734f5b54035ef2e61706b83041f20c. This dealigns the .dtsi from linux and seems fragile at the next synchronisation. 3- Change the clock list in rk3399-u-boot.dtsi or somewhere else. This survives .dts* sync but may survive "too much" and miss some change from linux that we might want. 4- Enable CONFIG_USB_OHCI_GENERIC and use the ports in USB 1 mode. This would need to be made for all boards using rk3399. In a simple test reading one file from USB storage it gave 769.5 KiB/s instead of 20.5 MiB/s with solution 2. 5- Trying to replicate linux and have usb2phy somehow provide a clk, or have a separate clock device for usb2phy in addition to the phy device. This patch tries to implement option 5 as Marek Vasut requested in December 5th. Options 1 and 3 didn't get through [2][3]. It just registers usb2phy as a clock driver (device_bind_driver() didn't work but device_bind_driver_to_node() did), without any specific operations, so that ehci-generic.c finds it and is happy. It worked in my tests on a Rock Pi 4 B+ (rk3399). Link: [1] https://lkml.kernel.org/lkml/1731551.Q6cHK6n5ZM@phil/T/ [2] https://patchwork.ozlabs.org/project/uboot/patch/20220701185959.GC1700@begut/ [3] https://patchwork.ozlabs.org/project/uboot/patch/Y44+ayJfUlI08ptM@localhost/ Cc: Simon Glass <sjg@chromium.org> Cc: Philipp Tomsich <philipp.tomsich@vrull.eu> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Lukasz Majewski <lukma@denx.de> Cc: Sean Anderson <seanga2@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Christoph Fritz <chf.fritz@googlemail.com> Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Xavier Drudis Ferran <xdrudis@tinet.cat> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # rk3399, rk3328, rv1126
2023-06-07usb: musb-new: sunxi: fix error checkSam Edwards
The `musb_register` function returns some ERR_PTR(...) on failure, not NULL, so update the check here appropriately. Signed-off-by: Sam Edwards <CFSworks@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de>
2023-06-07serial: meson: fix meson_serial_pending() tx logicMattijs Korpershoek
According to the dm_serial_ops documentation, pending() should: > @return number of waiting characters, 0 for none, -ve on error And: > It is acceptable to return 1 if an indeterminant number > of characters is waiting. With the current implementation, we have: * FIFO is full -> pending() returns 0 * FIFO is partially used -> pending() returns 1 * FIFO is empty -> pending() returns 1 This is not the same as what the documentation requires. Moreover, since [1], arm reset now flushes all console devices (including serial) before the cpu gets reset. Because of the flawed logic: => reset # user calls reset flush() is called _serial_flush() is called ops->pending(dev, false) # never returns false # board hangs indefinitely without resetting. Fix it by using AML_UART_TX_EMPTY instead of AML_UART_TX_FULL. [1] commit c5f4cdb8eb60 ("console: Use flush() before panic and reset"), Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230606-fix-meson-serial-pending-v1-1-6a54d4a01f76@baylibre.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-06-05I2C: cdns: Fix broken retry mechanism on arbitration lost.Andrea Merello
In the current implementation, in case of I2C arbitration lost, a retry is attempted; the message counter and pointer are reset to the original values and the I2C xfer process is restart from the beginning. However the message counter and message pointer are respectively decremented and incremented by one before attempting any transfer, causing the 1st transfer not to be actually retried (in case of a single transfer, nothing is actually retried at all). This patch fixes this: in case of retry, the 1st transfer is also retried. Tested on a ZynqMP Kria board, with upstream older u-boot, but the involved file and underlying logic seem basically the same. Signed-off-by: Andrea Merello <andrea.merello@iit.it>
2023-06-05i2c: rockchip: De-initialize the bus after start bit failureOndrej Jirman
Failure can happen when i2c is used without initializing pinctrl properly, which U-Boot happily allows in SPL. Without this fix, further I2C access would fail, even after proper pinctrl initialization. Signed-off-by: Ondrej Jirman <megi@xff.cz> Cc: Heiko Schocher <hs@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2023-05-30pci: apple: Add support for M2 Pro/MaxMark Kettenis
The PCIe controller on the M2 Pro/Max is different from the one found on earlier Apple SoCs. Some registers moved and te meaning of the bits in some other registers changed. But they are still similar enough to handle both controllers in the same driver. Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2023-05-25Merge tag 'u-boot-imx-20230525' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20230525 ------------------- - i.MX93 series - Fixes CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/16412
2023-05-21serial: mxs: Add MXS AUART driverMarek Vasut
Add trivial driver for the MXS AUART IP. This is the other UART IP present in i.MX23 and i.MX28, used to drive the non-DUART ports. Signed-off-by: Marek Vasut <marex@denx.de>
2023-05-21ddr: imx9: update the rank setting for multi fsp supportJacky Bai
The rank setting flow should be updated to support multi fsp config. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21ddr: imx93: update the ddr init to support mult setpointsJacky Bai
Update the DDR init flow for multi-setpoint support on i.MX93. A new fsp_cfg struct need to be added in the timing file to store the diff part of the DDRC and DRAM MR register for each setpoint. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21ddr: imx93: Add 625M bypass clock supportJacky Bai
Add 625M bypass clock that may be used DRAM 625M bypass mode support. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21ddr: imx9: Change the saved ddr data base to 0x2051c000Jacky Bai
change the ddr saved info to the last 16KB of the OCRAM. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21ddr: imx9: Add workaround for DDRPHY rank-to-rank errataYe Li
According to DDRPHY errata, the Rank-to-Rank Spacing and tphy_rdcsgap specification does not include the Critical Delay Difference (CDD) to properly define the required rank-to-rank read command spacing after executing PHY training firmware. Following the errata workaround, at the end of data training, we get all CDD values through the MessageBlock, then re-configure the DDRC timing of WWT/WRT/RRT/RWT with comparing MAX CDD values. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: add i.MX93 variants supportPeng Fan
According to datasheet, iMX93 has fused parts with CORE1 or NPU or both disabled. So update code to support it, the kernel device tree runtime update will be added in future patches. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21watchdog: ulp_wdog: guard reset_cpu with condition checkPeng Fan
There will be build error if CONFIG_SYSRESET is enabled, so guard the reset_cpu with condition check here Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Stefan Roese <sr@denx.de>
2023-05-21imx: imx8_cpu: print cpu grade temperaturePeng Fan
Support print out cpu grade temperature Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx: imx8_cpu: support get temperature for i.MX9Peng Fan
Use CONFIG_DM_THERMAL to make the temperature function could be reused by i.MX8 and i.MX9 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx: imx8_cpu: support i.MX9Peng Fan
Add CPU_IMX Kconfig Support imx8_cpu driver for i.MX9 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx: imx8_cpu: use static for local functionsPeng Fan
For local functions, use static for function. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx: move imx8 sci header file to include/firmware/imxPeng Fan
Move imx8 sci header file to include/firmware/imx, then we could use build macro to reuse some i.MX8 drivers for i.MX9, such as drivers/cpu/imx8_cpu.c. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Stefano Babic <sbabic@denx.de>
2023-05-21thermal: imx_tmu: Update TMU driver to support iMX93Ye Li
The TMU used on iMX93 is IP revision 2.1 which is different with previous revision used on iMX8MQ. So add a new FLAG V4 for this revision to distinguish the operations. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21thermal: imx_tmu: Move architecture code into driverMarek Vasut
Stop polluting the architecture directory with driver specific code, move it into driver where it should be. Split the code slightly so the MX8MM/MX8MN fuse readout and programming and MX8MP fuse readout and programming are in their separate functions, and called in case of matching SoC. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2023-05-21thermal: imx_tmu: Clean up all printsMarek Vasut
Use dev_(dev, ...) for all printing and debug logging, since this already includes the device name. Drop device name where duplicate. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2023-05-18spi: rockchip_sfc: Use linux rockchip,sfc-no-dma propJonas Karlman
Use the same prop as linux to control the use of fifo or dma mode. Also add a u-boot,spl-sfc-no-dma prop to control the same in SPL. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18mmc: rockchip_sdhci: Disable DMA mode using a device tree propertyJonas Karlman
Loading part of TF-A into SRAM from eMMC using DMA fails on RK3399 similar to other Rockchip SoCs. Checksum validation fails with: ## Checking hash(es) for Image atf-2 ... sha256 error! Bad hash value for 'hash' hash node in 'atf-2' image node spl_load_simple_fit: can't load image loadables index 1 (ret = -1) mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ### Add a device tree property, u-boot,spl-fifo-mode, to control when the rockchip_sdhci driver should disable the use of DMA and fallback on PIO mode. Same device tree property is used by the rockchip_dw_mmc driver. In commit 2cc6cde647e2 ("mmc: rockchip_sdhci: Limit number of blocks read in a single command") the DMA mode was disabled using a CONFIG option on RK3588. Revert that and instead disable DMA using the device tree property for all RK3588 boards, also apply similar workaround for all RK3399 boards. Fixes: 2cc6cde647e2 ("mmc: rockchip_sdhci: Limit number of blocks read in a single command") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Quentin Schulz <foss+uboot@0leil.net> # RK3399 Puma, RK3588 Tiger
2023-05-18mmc: rockchip_sdhci: Skip blocks read workaround on RK3399Jonas Karlman
The workaround to limit number of blocks to read in a single command should only be applied to RK3568 and RK3588. Change to be more strict when to apply the workaround. Fixes: 2cc6cde647e2 ("mmc: rockchip_sdhci: Limit number of blocks read in a single command") Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Quentin Schulz <foss+uboot@0leil.net> # RK3399 Puma, RK3588 Tiger
2023-05-17phy: rockchip: naneng-combphy: Support rk3588Jon Lin
Add support for rk3588 phy variant. The PHY clock is fixed at 100MHz. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> [kever.yang@rock-chips.com: update pcie pll parameters] Co-developed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> [eugen.hristev@collabora.com: squashed, tidy up] Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-17phy: rockchip: naneng-combphy: Add support for multiple resetsEugen Hristev
Some variants of the PHY have more than just one reset. To cover all cases, request the rests in bulk rather than just the reset at index 0. Co-developed-by: Ren Jianing <jianing.ren@rock-chips.com> Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-17pci: pcie_dw_rockchip: Support max_link_speed dts propertyJon Lin
Add support for max_link_speed specified in the PCI DT binding. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> [eugen.hristev@collabora.com: port to latest API, set default correctly, align to 80 chars] Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> [jonas@kwiboo.se: switch to dev_read_u32_default] Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-17pci: pcie_dw_rockchip: Add rk3588 compatibleJon Lin
Add compatible for RK3588 SoC. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-17reset: rockchip: implement rk3588 lookup tableEugen Hristev
The current DT bindings for the rk3588 clock use a different ID than the one that is supposed to be written to the hardware registers. Thus, we cannot use directly the id provided in the phandle, but rather use a lookup table to correctly setup the hardware. This approach has been implemented already in Linux, by commit : f1c506d152ff ("clk: rockchip: add clock controller for the RK3588") Hence, implement a similar approach using the lookup table, and adapt the existing reset driver to work with SoCs using lookup table. The file rst-rk3588.c has been copied as much as possible from Linux. Adapt the clk rk3588 driver as well to bind the reset driver with the lookup table. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-05-17phy: Keep balance of counts when ops is missingJonas Karlman
Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Fixes: 226fce6108fe ("phy: Track power-on and init counts in uclass") Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2023-05-17phy: rockchip-inno-usb2: add initial support for rk3588 PHYEugen Hristev
Add initial support for the rk3588 PHY variant. The lookup for the host-port reg inside the struct now does a do {} while() instead of a while() {} in order to allow a first check for reg == 0. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Co-developed-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-05-17phy: remove phy-supply related codeEugen Hristev
phy-supply is now handled at uclass level. Remove it from the drivers that implement it at the driver level. Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Suggested-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-05-17phy: add support for phy-supplyEugen Hristev
Some phys require a phy-supply property that is a phandle to a regulator that needs to be enabled for phy operations. Implement basic supply lookup, enable and disabling, if DM_REGULATOR is available. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> [jonas@kwiboo.se: use regulator_set_enable_if_allowed and disable if power_on ops fails] Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-05-16Merge branch '2023-05-15-assorted-bugfixes'Tom Rini
- Merge in a long-standing fix for some exynos platforms, correct a Kconfig description, fix some env issues, fix an issue in devfdt_get_addr_size_index_ptr and look for "panel-timings" not "panel-timing" per upstream binding.
2023-05-16Merge tag 'xilinx-for-v2023.07-rc3' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2023.07-rc3 .mailmap - Fix Xilinx IDs ZynqMP: - Fix R5 split boot mode - DT fixes - sync with Linux Xilinx: - Enable virtio and RNG support - Enable ADI ethernet phy SPI/Zynq: - Fix dummy byte calculation
2023-05-15core: fdtaddr: use map_sysmem() as cast for the return (part 2)Johan Jonker
For the devfdt_get_addr_size_index_ptr() function use map_sysmem() function as cast for the return for use in sandbox. Signed-off-by: Johan Jonker <jbx6244@gmail.com>
2023-05-15drivers: core: ofnode: fix typo in panel timing decodeRaphael Gallais-Pou
In case where a single timing resolution is implemented in the device-tree, the property is named "panel-timing", as specify in Linux kernel binding file: Documentation/devicetree/bindings/display/panel/panel-common.yaml # Display Timings panel-timing: description: Most display panels are restricted to a single resolution and require specific display timings. The panel-timing subnode expresses those timings. $ref: panel-timing.yaml# display-timings: description: Some display panels support several resolutions with different timings. The display-timings bindings supports specifying several timings and optionally specifying which is the native mode. $ref: display-timings.yaml# Fixes: 0347cc773270 ("drivers: core: ofnode: Add panel timing decode.") Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-05-15Revert "mmc: s5p_sdhci: unset the SDHCI_QUIRK_BROKEN_R1B"Henrik Grimler
This reverts commit a034ec06ff1d558bbe11d5ee05edbb4de3ee2215. Commit 4a3ea75de4c5 ("Revert "mmc: sdhci: set to INT_DATA_END when there are data"") reverted the alternative fix that was added for Exynos 4 devices, causing an error when trying to boot from an sdcard: <...> Loading Environment from MMC... sdhci_send_command: Timeout for status update! mmc fail to send stop cmd <...> Re-add the quirk to allow booting from sdcards again. Signed-off-by: Henrik Grimler <henrik@grimler.se>
2023-05-15video: tweak CONFIG_SPL_VIDEO descriptionJohn Keeping
Make it clear that this is the SPL option to avoid potential confusion when the description for CONFIG_SPL_VIDEO is the same as that for CONFIG_VIDEO. Signed-off-by: John Keeping <john@metanate.com>
2023-05-15Merge https://source.denx.de/u-boot/custodians/u-boot-cfi-flashTom Rini
- cfi: respect reg address length (Nuno)
2023-05-15mtd: cfi: respect reg address lengthNuno Sá
flash_get_size() will get the flash size from the device itself and go through all erase regions to read protection status. However, the device mappable region (eg: devicetree reg property) might be lower than the device full size which means that the above cycle will result in a data bus exception. This change fixes it by reading the 'addr_size' during probe() and also use that as one possible upper limit. Signed-off-by: Nuno Sá <nuno.sa@analog.com>
2023-05-15Revert "spi: zynq_qspi: Use dummy buswidth in dummy byte calculation"Stefan Herbrechtsmeier
This reverts commit e09784728689de7949d4cdd559a9590e0bfcc702. The commit wrongly divides the dummy bytes by dummy bus width to calculate the dummy bytes. The framework already converts the dummy cycles to the number of bytes and the controller use the SPI flash command to determine the dummy cycles via the address width. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Acked-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230427065355.7413-1-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
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