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2023-02-28tpm: sandbox: Change the return code when device is already openIlias Apalodimas
All the TPM drivers as well as out TCG TIS API for a TPM2.0 device return -EBUSY if the device has already been opened. Adjust the sandbox TPM do return the same error code. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-02-27Merge tag 'v2023.04-rc3' into nextTom Rini
Prepare v2023.04-rc3
2023-02-23ARM: tegra: provide default USB gadget setupMaxim Schwalm
All Nvidia boards use the same manufacturer, vendor ID and product ID for the gadgets. Make them the defaults to remove some boilerplate from the defconfigs. Inspired by commit e02687bda96c ("sunxi: provide default USB gadget setup") which did the same for Allwinner boards. Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124 Signed-off-by: Maxim Schwalm <maxim.schwalm@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23spi: tegra20_slink: accept any word lengthSvyatoslav Ryhel
Original t20 slink could work with commands only fully divisible by 8. This patch removes such restriction, so commands of any bitlength now can be passed and processed. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra: Fix Tegra PWM parent clockSvyatoslav Ryhel
Default parent clock for the PWM on Tegra is a 32kHz clock and is unable to support the requested PWM period. Fix PWM support on Tegra20, Tegra30, Tegra114, Tegra124 and Tegra210 by updating the parent clock for the PWM to be the PLL_P. This commit is equivalent to Linux kernel commit: https://lore.kernel.org/all/20221010100046.6477-1-jonathanh@nvidia.com/ Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # ASUS TF201 T30 Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23usb: dwc3-uniphier: Select PHYMarek Vasut
Make sure the PHY subsystem is activated for the uniphier DWC3 glue logic, as it depends on PHY implementation there. Signed-off-by: Marek Vasut <marex@denx.de>
2023-02-22usb: dwc3-uniphier: Use dwc3-generic instead of xhci-dwc3Kunihiko Hayashi
dwc3-uniphier depends on xhci-dwc3 framework, however, it is preferable to use dwc3-generic. This driver calls the exported dwc3-generic functions and redefine the SoC-dependent operations to fit dwc3-generic. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22phy: socionext: Add UniPhier USB3 PHY driverKunihiko Hayashi
Add USB3 PHY driver support to control clocks and resets needed to enable PHY. The phy_ops->init() and exit() control PHY clocks and resets only, and clocks and resets for the controller and the parent logic are enabled in advance. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22clk: uniphier: Add missing USB SS-PHY clocksKunihiko Hayashi
The USB SS-PHY needs its own clock, however, some clocks don't have clock gates. Define missing clock entries for the PHY as reference clock. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22reset: uniphier: Add USB glue reset supportKunihiko Hayashi
Add reset control support in USB glue logic. This needs to control the external clocks and resets for the logic before accessing the glue logic. The USB dm tree when using dwc3-generic is the following: USB glue +-- controller (need controller-reset) +-- controller-reset (need syscon-reset) +-- phy The controller needs to deassert "controller-reset" in USB glue before the controller registers are accessed. The glue needs to deassert "syscon-reset" before the glue registers are accessed. The glue itself doesn't have "syscon-reset", so the controller-reset controls "syscon-reset" instead. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22usb: dwc3-generic: Add the size of regs property to glue structureKunihiko Hayashi
Add the size of regs property to the glue structure to correctly specify the register region to map. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22usb: dwc3-generic: Export glue structures and functionsKunihiko Hayashi
In order to allow external SoC-dependent glue drivers to use dwc3-generic functions, push the glue structures and export the functions to a header file. The exported structures and functions are: - struct dwc3_glue_data - struct dwc3_glue_ops - dwc3_glue_bind() - dwc3_glue_probe() - dwc3_glue_remove() The SoC-dependent glue drivers can only define their own wrapper driver and specify these functions. The drivers can also add their own compatible strings and configure functions. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22usb: dwc3-generic: Add clock initialization in child DT nodeKunihiko Hayashi
Same as the reset cotnrol, should add a clock initialization in child DT node, if the glue node doesn't have any clocks. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22usb: dwc3-generic: Allow different controller DT node patternKunihiko Hayashi
The most of devicetree has the following USB node structure. The controller node is placed as a child node of the glue node. Current dwc3-generic driver works on this premise. glue { /* glue node */ usb { /* controller node */ }; }; However, UniPhier original devicetree has the following USB node structure. The controller node is separately placed from the glue node. usb { /* controller node */ }; glue { /* glue node */ }; In dwc_glue_bind(), this patch provides .glue_get_ctrl_dev() callback to get such a controller node and binds the driver related to the node. If this callback isn't defined, dwc_glue_bind() looks for the controller nodes from the child nodes, as before. Suggested-by: Marek Vasut <marex@denx.de> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22usb: dwc3: Look up reference clock DT phandle in both controller DT nodesMarek Vasut
There are currently four disparate placement possibilities of DWC3 reference clock phandle in SoC DTs: - in top level glue node, with generic subnode without clock (ZynqMP) - in top level generic node, with no subnode (i.MX8MQ) - in generic subnode, with other clock in top level node (i.MX8MP) - in both top level node and generic subnode (Rockchip) Cover all the possibilities here by looking into both nodes, start with the top level node as that seems to be used in majority of DTs to reference the clock. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
2023-02-22usb: dwc3: Use the devm_gpiod_get_optional() API for reset gpioVenkatesh Yadav Abbarapu
As the "reset-gpios" property is optional, don't return the error and just skip the gpio reset sequence. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
2023-02-17cpsw_mdio.c: Use correct reg in cpsw_mdio_get_aliveUlf Samuelsson
cpsw_mdio_get_alive reads the wrong register. See page 2316 in SPRUH73Q AM335x TRM Signed-off-by: Ulf Samuelsson <ulf@emagii.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2023-02-17driver: cache-v5l2: Fix type casting warning on RV32Yu Chien Peter Lin
This patch fixes following warning for the riscv32 toolchain. drivers/cache/cache-v5l2.c:122:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 122 | regs = (struct l2cache *)dev_read_addr(dev); | ^ Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-02-17riscv: ae350: dts: Update L2 cache compatible stringYu Chien Peter Lin
Update the compatible string of L2 cache. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2 platformYu Chien Peter Lin
The L2C configuration register has MAP field to indicate its version is v0 (Gen1) or v1 (Gen2) L2-cache. This patch makes the driver compatible with both memory-mapped scheme. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"Leo Yu-Chi Liang
There is no need for RISCV_NDS_CACHE config to control cache switches. Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-14dm: treewide: Complete migration to new driver model schemaSimon Glass
Update various build and test components to use the new schema. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-14dm: Add support for handling old u-boot,dm- tagsSimon Glass
Add a CONFIG option to deal with this automatically, printing a warning when U-Boot starts up. This can be useful if the device tree comes from another project. We will maintain this through the 2023.07 release, providing 6 months for people to notice. Signed-off-by: Simon Glass <sjg@chromium.org> Version 4: Acked-by: Michal Simek <michal.simek@amd.com>
2023-02-13i2c: i2c-cdns.c: Update driver to read fifo-depth from device treePei Yue Ho
Enable driver to fetch the optional parameter (fifo-depth) from device tree. If the parameter is not found in the device tree, it will use the default value declared in the driver. Signed-off-by: Pei Yue Ho <peiyue.ho@starfivetech.com> Reviewed-by: Wei Liang Lim <weiliang.lim@starfivetech.com> Reviewed-by: Eng Lee Teh <englee.teh@starfivetech.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2023-02-13i2c:aspeed:support ast2600 i2c new register mode driverRyan Chen
Add i2c new register mode driver to support AST2600 i2c new register mode. AST2600 i2c controller have legacy and new register mode. The new register mode have global register support 4 base clock for scl clock selection, and new clock divider mode. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2023-02-13i2c: mxc_i2c: Use hex notation for the base addressFabio Estevam
Printing the I2C controller base address in decimal notation is not helpful. Change it to hex notation, which is the standard format found in the Reference Manual and devicetree. Signed-off-by: Fabio Estevam <festevam@denx.de> Acked-by: Dhruva Gole <d-gole@ti.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2023-02-12Merge tag 'clk-2023.04-rc1' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-clk Clock changes for 2023.04-rc1 This contains various fixes and small features. I've included a reset patch as well since it was in the same series as a clock patch.
2023-02-12Merge branch 'for-2023.04' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-mpc8xx - A fix for a long standing bug that has been exposed by commit 50128aeb0f8 ("cyclic: get rid of cyclic_init()") preventing 8xx boards from booting since u-boot 2023.01 - A GPIO driver for powerpc 8xx chip - Fixup for powerpc 8xx SPI driver - A new powerpc 8xx board - The two devices having that board.
2023-02-12reset: Allow reset_get_by_name() with NULL nameSamuel Holland
This allows devm_reset_control_get(dev, NULL) to work and get the first reset control, which is common in code ported from Linux. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20230122000252.53642-2-samuel@sholland.org
2023-02-12clk: Allow clk_get_by_name() with NULL nameSamuel Holland
This allows devm_clock_get(dev, NULL) to work and get the first clock, which is common in code ported from Linux. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20230122000252.53642-1-samuel@sholland.org
2023-02-12clk: imx8mn: fix imx8mn_enet_phy_sels clocks listDario Binacchi
[backport from linux commit 2626cf67f20b28446dfc3a5b9493dd535cdb747b] According to the "Clock Root" table of the reference manual (document IMX8MNRM Rev 2, 07/2022): Clock Root offset Source Select (CCM_TARGET_ROOTn[MUX]) ... ... ... ENET_PHY_REF_CLK_ROOT 0xAA80 000 - 24M_REF_CLK 001 - SYSTEM_PLL2_DIV20 010 - SYSTEM_PLL2_DIV8 011 - SYSTEM_PLL2_DIV5 100 - SYSTEM_PLL2_DIV2 101 - AUDIO_PLL1_CLK 110 - VIDEO_PLL_CLK 111 - AUDIO_PLL2_CLK ... ... ... while the imx8mn_enet_phy_sels list didn't contained audio_pll1_out for source select bits 101b. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Acked-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20221219113127.528282-4-dario.binacchi@amarulasolutions.com
2023-02-12clk: imx: rename video_pll1 to video_pllDario Binacchi
[backport from linux commit bedcf9d1dcf88ed38731f0ac9620e5a421e1e9d6] Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the name used in the RM is video_pll. So, let's rename "video_pll1" to "video_pll" to be consistent with the RM and avoid misunderstandings. No functional changes intended. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Acked-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20221219113127.528282-3-dario.binacchi@amarulasolutions.com
2023-02-12clk: imx8mn: rename vpu_pll to m7_alt_pllDario Binacchi
[backport from linux commit a429c60baefd95ab43a2ce7f25d5b2d7a2e431df] The IMX8MN platform does not have any video processing unit (VPU), and indeed in the reference manual (document IMX8MNRM Rev 2, 07/2022) there is no occurrence of its pll. From an analysis of the code and the RM itself, I think vpu pll is used instead of m7 alternate pll, probably for copy and paste of code taken from modules of similar architectures. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Acked-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20221219113127.528282-2-dario.binacchi@amarulasolutions.com
2023-02-12clk: nuvoton: fix bug for calculate pll clockJim Liu
Fix bug for npcm7xx bmc calculate pll clock. PLLCON1 need to divide by 2. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Acked-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20221121091528.1351-1-JJLIU0@nuvoton.com
2023-02-11timer: Tidy up use of notraceSimon Glass
Tracing is typically enabled by the time driver model starts up, so there is no point in adding a 'notrace' to the timer-init function. However, once the driver model timer is enabled, we do need to be able to access the timer's private data when reading the timer, so add it to the core function needed for that. Update the function's documentation while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-11usb: gadget: Fix typo in obj lineTom Rini
When dropping the unused fotg210 gadget driver a leading 0 was introduced to the next line, drop it. Fixes: e9b4678bc78e ("usb: Drop unused fotg210 gadget") Reported-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2023-02-11spi, mpc8xx: Add support for chipselect via GPIO and fixupsChristophe Leroy
This patch fixes the mpc8xx SPI driver: - A stub callbacks for mode and speed, - Use chip selects defined as GPIOs, - Write proper value to disable relocation, other it fails on mpc885, - Don't modify ports setup, ports can be different from one board to another and are already set by board_early_init_r(). This patch was originally written by Charles Frey who's email address is not valid anymore as he left the company. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Reviewed-by: FRANJOU Stephane <stephane.franjou@csgroup.eu>
2023-02-11driver, gpio: Add support for MPC 8xx CPU portsChristophe Leroy
Ports A, C and D are 16 bits ports. Ports B and E are 32 bits ports. The "compatible" is used to determine each port type. This patch was originally written by Charles Frey who's email address is not valid anymore as he left the company. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Reviewed-by: FRANJOU Stephane <stephane.franjou@csgroup.eu>
2023-02-10net: ftmac100: add mii read and write callbacksSergei Antonov
Register mii_bus with read and write callbacks to allow the 'mii' command to work. Use a timeout of 10 ms to wait for the R/W operations to complete. Signed-off-by: Sergei Antonov <saproj@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Tested-by: Rick Chen <rick@andestech.com>
2023-02-10net: ftmac100: simplify priv->iobase castingSergei Antonov
Replace 'phys_addr_t iobase' with 'struct ftmac100 *ftmac100' in struct ftmac100_data. It allows to remove casting in a number of places. Since priv->iobase is phys_addr_t, use phys_to_virt() to make a pointer from it. Signed-off-by: Sergei Antonov <saproj@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-10net: ftmac100: change driver name from nds32_mac to ftmac100Sergei Antonov
So it will be named similarly to the related ftgmac100 driver. The old name 'nds32_mac' is not referred to anywhere in U-Boot. Signed-off-by: Sergei Antonov <saproj@gmail.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-10dm: input: add button_kbd driverDzmitry Sankouski
Bootmenu requires an input device with arrows and enter key. A common smartphone luckily has power, volume up/down buttons, which may be used for controlling bootmenu. To use driver, add 'button-kbd' to stdin. Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-10dm: button: add support for linux_code in button-gpio.c driverDzmitry Sankouski
Linux event code must be used in input devices, using buttons. Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-10gpio: qcom: add direction functions for pwrkeyDzmitry Sankouski
GPIO button driver requires direction functions to probe button gpio. Those functions are blank, since pwrkey is not really gpio, and don't support direction settings. Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
2023-02-10i2c: Add support for Qualcomm I2C driverSumit Garg
Add support for Qualcomm I2C QUP driver which is inspired from corresponding driver in Linux: drivers/i2c/busses/i2c-qup.c. Currently this driver only support FIFO polling mode which is sufficient to support devices like eeprom, rtc etc. Co-developed-by: Mike Worsfold <mworsfold@impinj.com> Signed-off-by: Mike Worsfold <mworsfold@impinj.com> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2023-02-10net: dwc_eth_qos: Add Qcom ethernet driver glue layerSumit Garg
The Qualcom ETHQOS hardware supports an RGMII macro which needs to be configured according to following link speeds: - SPEED_1000 - SPEED_100 - SPEED_10 So add a corresponding glue driver to configure RGMII macro. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-02-10net: dwc_eth_qos: Allow platform to override tx/rx_fifo_szSumit Garg
The GMAC controller on QCS404 SoC (support added by upcoming patch) fails to work with maximum tx/rx_fifo_sz supported by the hardware (16K). So allow platforms to override FIFO size using corresponding DT node properties. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-02-10net: dwc_eth_qos: Make eqos_get_tick_clk_rate callback optionalSumit Garg
Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-02-10Correct SPL use of ATMEL_PIO4Simon Glass
This converts 1 usage of this option to the non-SPL form, since there is no SPL_ATMEL_PIO4 defined in Kconfig Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10Correct SPL use of PANELSimon Glass
This converts 1 usage of this option to the non-SPL form, since there is no SPL_PANEL defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org>
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