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2022-06-29mtd: mxs_nand_spl: fix nand_command protocol violationAndrea Scian
mxs_nand_command() implementation assume that it's working with a LP NAND, which is a common case nowadays and thus uses two bytes for column address. However this is wrong for NAND_CMD_READID and NAND_CMD_PARAM, which expects only one byte of column address, even for LP NANDs. This leads to ONFI detection problem with some NAND manufacturer (like Winbond) but not with others (like Samsung and Spansion) We fix this with a simple workaround to avoid the 2nd byte column address for those two commands. Also align the code with nand_base to support 16 bit devices. Tested on an iMX6SX device with: * Winbond W29N04GVSIAA * Spansion S34ML04G100TF100 * Samsung K9F4G08U00 Tested on imx8mn device with: * Windbond W29N04GV Signed-off-by: Andrea Scian <andrea.scian@dave.eu> CC: Stefano Babic <sbabic@denx.de> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-06-28pmic: pca9450: Add optional SD_VSEL GPIO for LDO5Frieder Schrempf
LDO5 has two separate control registers. LDO5CTRL_L is used if the input signal SD_VSEL is low and LDO5CTRL_H if it is high. The current driver implementation only uses LDO5CTRL_H. To make this work on boards that have SD_VSEL connected to a GPIO, we add support for specifying an optional GPIO and setting it to high at probe time. In the future we might also want to add support for boards that have SD_VSEL set to a fixed low level. In this case we need to change the driver to be able to use the LDO5CTRL_L register. This is a port of the same change in the Linux kernel: 8c67a11bae88 ("regulator: pca9450: Add SD_VSEL GPIO for LDO5") Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Fabio Estevam <festevam@denx.de> Tested-by: Fabio Estevam <festevam@denx.de>
2022-06-26clk: sunxi: Add additional RTC compatible stringsSamuel Holland
Compatible strings for some new RTC hardware variants were added to the binding. Add them to the driver in preparation for supporting those new SoCs. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-06-26gpio: sunxi: Fix build with CONFIG_SPL_SERIAL=nSamuel Holland
This driver uses simple_strtol(), so it needs SPL_STRTO. Before commit 88ca8e26958b6 ("disk: Add an option for partitions in SPL"), SPL_STRTO was always selected indirectly. Now it is not, so select it here. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-06-26sunxi: usb: convert PHY GPIO functions to DMAndre Przywara
The Allwinner USB PHY driver is still using the legacy GPIO interface, which is now implemented by the DM_GPIO compat functions. Those seem to have some design flaws, as setting the direction, then later setting the value will not work, if the DM_GPIO driver is implementing set_flags. Fix this by using the dm_ version of the direct GPIO interface, which uses struct gpio_desc structs to handle requested GPIOs, and actually keeps the flags we set earlier. This fixes USB operation on boards which need to toggle the VBUS supply via a GPIO, like the Teres-I laptop or the BananaPi M2 Berry board. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reported-by: Milan P. Stanić <mps@arvanta.net> Reviewed-by: Samuel Holland <samuel@sholland.org>
2022-06-25video: stm32: remove test on CONFIG_DM_REGULATORPatrick Delaunay
The tests on CONFIG_DM_REGULATOR, added to avoid compilation issues, can now be removed, they are no more needed since the commit 16cc5ad0b439 ("power: regulator: add dummy helper"). Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-06-25driver: video: Check allocated pointersBin Meng
The codes that call STBTT_malloc() / stbtt__new_active() do not check the return value at present which may cause segfault. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2022-06-23arm: apple: nvme: Add SART support and RTKit buffer managementJanne Grunau
The NVMe firmware in the macOS 13 beta blocks or crashes with u-boot's current minimal RTKit implementation. It does not provide buffers for the firmware's buffer requests. The ANS2 firmware included in macOS 11 and 12 tolerates this. The firmware included in the first macOS 13 beta requires buffers for the crashlog and ioreport endpoints to function. In the case of the NVMe the buffers are physical memory. Access to physical memory is guarded by what Apple calls SART. Import m1n1's SART driver (exclusively used for the NVMe controller). Implement buffer management helpers for RTKit. These are generic since other devices (none in u-boot so far) require different handling. Signed-off-by: Janne Grunau <j@jannau.net> Reviewed-by: Mark Kettenis <kettenis@openbsd.org> Tested-by: Mark Kettenis <kettenis@openbsd.org>
2022-06-17Merge commit '32e0379143b433e29d76404f5f4c279067e48853' of ↵Tom Rini
https://github.com/tienfong/uboot_mainline
2022-06-17ddr: altera: soc64: Integer fix overflow that caused DDR size mismatchedDinesh Maniyam
Convert the constant integer to 'phys_size_t' to avoid overflow when calculating the SDRAM size. Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-17drivers: cache: ncore: Disable snoop filterDinesh Maniyam
There is hardware bug in NCORE CCU IP and it is causing an issue in the coherent directory tracking of outstanding cache lines. The workaround is disabling snoop filter. Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-16usb: host: ehci-generic: Make resets and clocks optionalAndre Przywara
The generic EHCI binding does not *require* resets and clocks properties, and indeed for instance the Allwinner A20 SoCs does not need or define any resets in its DT. Don't easily give up if clk_get_bulk() or reset_get_bulk() return an error, but check if that is due to the DT simply having no entries for either of them. This fixes USB operation on all boards with an Allwinner A10 or A20 SoC, which were reporting an error after commit ba96176ab70e2999: ======================= Bus usb@1c14000: ehci_generic usb@1c14000: Failed to get resets (err=-2) probe failed, error -2 ======================= Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-16crypto: fsl_hash: Remove unnecessary alignment check in caam_hash()Stefan Roese
While working on an LX2160 based board and updating to latest mainline I noticed problems using the HW accelerated hash functions on this platform, when trying to boot a FIT Kernel image. Here the resulting error message: Using 'conf-freescale_lx2160a.dtb' configuration Trying 'kernel-1' kernel subimage Verifying Hash Integrity ... sha256Error: Address arguments are not aligned CAAM was not setup properly or it is faulty error! Bad hash value for 'hash-1' hash node in 'kernel-1' image node Bad Data Hash ERROR: can't get kernel image! Testing and checking with Gaurav Jain from NXP has revealed, that this alignment check is not necessary here at all. So let's remove this check completely. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Gaurav Jain <gaurav.jain@nxp.com> Cc: dullfire@yahoo.com Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com>
2022-06-16Merge tag 'u-boot-imx-20220616' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20220616 ------------------- Fixes for 2022.07 + Toradex apalis-imx8 (missed in last PR) CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/12322
2022-06-16ddr: altera: Stratix10: Use phys_size_t for memory sizeTien Fong Chee
Replace with phys_size_t for all memory size variables declaration for the sake of scalability. phys_size_t is defined in /arch/arm/include/asm/types.h. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-16ddr: altera: Ignore bit[7-4] for both seq2core & core2seq handshake in HPSTien Fong Chee
Bit[7-4] for both register seq2core and core2seq handshake in HPS are not required for triggering DDR re-calibration or resetting EMIF. So, ignoring these bits just for playing it safe. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-15Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-pmicTom Rini
2022-06-15intel: n5x: ddr: update licenseTien Fong Chee
All the source code of sdram_n5x.c are from Intel, update the license to use both GPL2.0 and BSD-3 Clause because this copy of code may used for open source and internal project. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-15spi: nxp_fspi: Fix clock imbalanceMarek Vasut
The nxp_fspi_default_setup() is only ever called from nxp_fspi_probe(), where the IP clock are initially disabled. Drop the second disabling of clock to prevent clock enable/disable imbalance reported by clock core: " clk qspi_root_clk already disabled " Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-06-15mmc: fsl_esdhc_imx: Implement wait_dat0 mmc opsLoic Poulain
Implement wait_dat0 mmc ops callbac, allowing to reduce SPL boot time. Before (using grabserial): [0.000001 0.000001] U-Boot SPL 2021.04-xxxx [0.028257 0.028257] DDRINFO: start DRAM init [0.028500 0.000243] DDRINFO: DRAM rate 3000MTS [0.304627 0.276127] DDRINFO:ddrphy calibration done [0.305647 0.001020] DDRINFO: ddrmix config done [0.352584 0.046937] SEC0: RNG instantiated [0.374299 0.021715] Normal Boot [0.374675 0.000376] Trying to boot from MMC2 [1.250580 0.875905] NOTICE: BL31: v2.4(release):lf-5.10.72-2.2.0-0-g5782363f9 [1.251985 0.001405] NOTICE: BL31: Built : 08:02:40, Apr 12 2022 [1.522560 0.270575] [1.522734 0.000174] [1.522788 0.000054] U-Boot 2021.04-xxxx After: [0.000001 0.000001] U-Boot SPL 2021.04-xxxx [0.001614 0.001614] DDRINFO: start DRAM init [0.002377 0.000763] DDRINFO: DRAM rate 3000MTS [0.278494 0.276117] DDRINFO:ddrphy calibration done [0.279266 0.000772] DDRINFO: ddrmix config done [0.338432 0.059166] SEC0: RNG instantiated [0.339051 0.000619] Normal Boot [0.339431 0.000380] Trying to boot from MMC2 [0.412587 0.073156] NOTICE: BL31: v2.4(release):lf-5.15.5-1.0.0-0-g05f788b [0.414191 0.001604] NOTICE: BL31: Built : 10:35:26, Apr 6 2022 [0.700685 0.286494] [0.700793 0.000108] [0.700845 0.000052] U-Boot 2021.04-xxxx Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-06-15mmc: Add support for wait_dat0 callbackLoic Poulain
There is no wait_dat0 mmc ops, causing operations waiting for data line state change (e.g mmc_switch_voltage) to fallback to a 250ms active delay. mmc_ops still used when DM_MMC is not enabled, which is often the case for SPL. The result can be unexpectly long SPL boot time. This change adds support for wait_dat0() mmc operation. Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-06-15mmc: fix error message for unaligned erase requestPatrick Delaunay
Fix the end address in the message for unaligned erase request in mmc_berase() when start + blkcnt is aligned to erase_grp_size. for example: - start = 0x2000 - 26 - count = 26 - erase_grp_size = 0x400 Caution! Your devices Erase group is 0x400 The erase range would be change to 0x2000~0x27ff But no issue when the end address is not aligned, for example - start = 0x2000 - 2 * 26 - count = 26 - erase_grp_size = 0x400 Caution! Your devices Erase group is 0x400 The erase range would be change to 0x2000~0x23ff Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-14clk: imx8mp: use usb_core_ref for usb_root_clkAndrey Zhizhikin
Upstream commit 7a2c3be95a50 ("clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clock") added usb_core_ref for USB Controller but never set it to be used as a clock source, using rather "osc_32k" instead. This produces following boot log message: "clk_register: failed to get osc_32k device (parent of usb_root_clk)" Fix the USB controller clock source by using usb_core_ref instead of osc_32k. Fixes: 7a2c3be95a50 ("clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clock") Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-06-14clk: imx8mp: fix root clock names for ecspiAndrey Zhizhikin
Root clock name contained underscore, which does not match to the actual clock name. Correct the name to match what is present in the FDT. Fixes: 87f958810fcb ("clk: imx8mp: Add ECSPI clocks") Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: uboot-imx <uboot-imx@nxp.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-06-14phy: adin: add support for clock outputJosua Mayer
The ADIN1300 supports generating certain clocks on its GP_CLK pin, as well as providing the reference clock on CLK25_REF. Add support for selecting the clock via device-tree properties. This patch is based on the Linux implementation for this feature, which has been added to netdev/net-next.git [1]. [2] https://patchwork.kernel.org/project/netdevbpf/cover/20220517085143.3749-1-josua@solid-run.com/ Signed-off-by: Josua Mayer <josua@solid-run.com>
2022-06-14phy: adin: fix broken support for adi, phy-mode-overrideNate Drude
Currently, the adin driver fails to compile. The original patch introducing the adin driver used the function phy_get_interface_by_name to support the adi,phy-mode-override property. Unfortunately, a few days before the adin patch was accepted, another patch removed support for phy_get_interface_by_name: https://github.com/u-boot/u-boot/commit/123ca114e07ecf28aa2538748d733e2b22d8b8b5 This patch refactors adin_get_phy_mode_override, implementing the logic in the new function, ofnode_read_phy_mode, from the patch above. Signed-off-by: Nate Drude <nate.d@variscite.com> Tested-by: Josua Mayer <josua@solid-run.com> Signed-off-by: Josua Mayer <josua@solid-run.com>
2022-06-14pmic: pca9450: add DM_I2C dependencies in KconfigRasmus Villemoes
The pca9450 driver uses dm_i2c_{read,write}, which are (unsurprisingly) only available with DM_I2C. Make sure one can't create an unbuildable .config by adding proper dependencies. While here, append "in SPL" to the prompt for the SPL_ variant so it doesn't read the same as the one for the non-SPL_ variant. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-06-13arm: tegra: Update some DT compatiblesPeter Robinson
Some of the DT compatibles have changed upstream so add new DT compatibles to ensure things continue to keep working if the device trees are updated. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2022-06-13pci: tegra: Update error prints with new linesPeter Robinson
Add new lines to make errorr messages easier to read. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2022-06-07misc: Port USB251xB/xBi Hi-Speed Hub Controller Driver from LinuxMarek Vasut
This patch adds a driver for configuration of the Microchip USB251xB/xBi USB 2.0 hub controller series with USB 2.0 upstream connectivity, SMBus configuration interface and two to four USB 2.0 downstream ports. This is ported from Linux as of Linux kernel commit 5c2b9c61ae5d8 ("usb: usb251xb: add boost-up property support") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Simon Glass <sjg@chromium.org>
2022-06-07usb: xhci-mtk: disable all ports when disable host controllerChunfeng Yun
This is used to avoid the ports status of IPPC being brought in kernel stage, it may cause ports error especially when the xhci controller is a component of dual-role controller. Reported-by: Yun-Chien Yu <yun-chien.yu@mediatek.com> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
2022-06-03net: enetc: unregister mdiobusMichael Walle
If the device fails to probe - for example, when there is no ethaddr set - then the private data is automatically freed but the mdiobus remains registered. Fixes: 1e354cb39314 ("drivers: net: fsl_enetc: register internal MDIO bus") Signed-off-by: Michael Walle <michael@walle.cc>
2022-05-26net: e1000: Depend on CONFIG_PCISean Anderson
This driver depends on PCI. Update the Kconfig accordingly. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-05-25Merge tag 'xilinx-for-v2022.07-rc4' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2022.07-rc4 zynqmp: - Fix DP PLL configuration for zcu102/zcu106 and SOM - Fix split mode for starting R5s - DT fixes - Remove firmware node for mini configurations - Wire TEE for multi DTB fit image xilinx: - Handle board_get_usable_ram_top(0) properly phy: - Extend psgtr timeout mmc: - Fix mini configuration which misses zynqmp_pm_is_function_supported()
2022-05-24Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini
The bulk of it is (finally!) some DT sync from the kernel. We refrained from syncing one incompatible change, as this would spoil booting Linux kernels before v5.13 with U-Boot's DT (via UEFI, for instance). I test booted Linux v5.18 and v5.4 with that new DT on some boards, and the headless peripherals (MMC, USB, Ethernet) seemed to work. The rest are fixes: - silencing missing clock warnings due to the new pinctrl driver - fixing "UART0 on PortF", allowing UART access through the SD card pins - add an F1C100s clock driver, to enable MMC support (SPI comes later) - some cleanups for CONS_INDEX_n in Kconfig Tested on BananaPi-M1, Pine64-LTS, Pine-H64, X96-Mate (H616) and OrangePi-Zero.
2022-05-24Merge tag 'tpm-24052022' of https://source.denx.de/u-boot/custodians/u-boot-tpmTom Rini
Add support for i2c devices
2022-05-24serial: Remove obsolete CONS_INDEX_n Kconfig optionsSamuel Holland
These were only ever implied by sunxi platforms, and that usage has been removed. Current practice is to specify CONFIG_CONS_INDEX in each board's defconfig. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-24clk: sunxi: add and use dummy gate clocksAndre Przywara
Some devices enumerate various clocks in their DT, and many drivers just blanketly try to enable all of them. This creates problems since we only model a few gate clocks, and the clock driver outputs a warning when a clock is not described: ========= sunxi_set_gate: (CLK#3) unhandled ========= Some clocks don't have an enable bit, or are already enabled in a different way, so we might want to just ignore them. Add a CCU_CLK_F_DUMMY_GATE flag that indicates that case, and define a GATE_DUMMY macro that can be used in the clock description array. Define a few clocks, used by some pinctrl devices, that way to suppress the runtime warnings. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org>
2022-05-24clk: sunxi: add PIO bus gate clocksAndre Przywara
The introduction of the DM pinctrl driver made its probe function enable all clocks enumerated in the DT. This includes the "CLK_BUS_PIO" (and variations) gate clock. Also CLK_PLL_PERIPH0 is used by the R_CCU device. So far we didn't describe those clocks in our clock driver. As we enable them already in the SPL, the devices happen to work, but the clock driver still complains about not finding those clocks: ========= sunxi_set_gate: (CLK#58) unhandled ========= Add the one-liners that are needed to announce the gate bit for those clocks, to silence that message on the console. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org>
2022-05-24clk: sunxi: h6_r: Correct the driver nameSamuel Holland
H6 is from the sun50i family, not sun6i. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-24mmc: sunxi: Remove unnecessary pinmux option dependencySamuel Holland
Now that the pinmux conflict is handled in the board code (by skipping setup for the one conflicting MMC controller), the driver does not need to be entirely disabled based on the UART pinmux. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-23tpm: add support for TPMv2.x I2C chipsEddie James
Add the tpm2_tis_i2c driver that should support any TPMv2 compliant I2C chips, such as the NPCT75X chip. [Ilias rename priv_auto_alloc_size to priv_auto] Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-05-23mmc: fsl_esdhc_spl: Fix checking for number of read sectorsPali Rohár
Commit 0980cbba7b3c ("mmc: fsl_esdhc_spl: pre-PBL: implement redundancy support") changed number of sectors which are read but did not adjusted error check. Fix it and check for if correct number of sectors were read. Fixes: 0980cbba7b3c ("mmc: fsl_esdhc_spl: pre-PBL: implement redundancy support") Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-05-23spi: spi_flash_probe_bus_cs() rely on DT for spi speed and modePatrice Chotard
Now, spi_flash_probe_bus_cs() relies on DT for spi speed and mode and logically calls spi_get_bus_and_cs(). In case spi mode and speed are not read from DT, make usage of spi_flash_probe() instead. To sum-up: - Previous call tree was: spi_flash_probe() -> spi_flash_probe_bus_cs() -> spi_get_bus_and_cs() - Current call tree is: spi_flash_probe() -> _spi_get_bus_and_cs() spi_flash_probe_bus_cs() -> spi_get_bus_and_cs() This patch impacts the following : - cmd/sf.c: if spi mode and/or speed is passed in argument of do_spi_flash_probe(), call spi_flash_probe() otherwise call spi_flash_probe_bus_cs(). - drivers/net/fm/fm.c: as by default spi speed and mode was set to 0 and a comment indicates that speed and mode are read from DT, use spi_flash_probe_bus_cs(). - drivers/net/pfe_eth/pfe_firmware.c: spi speed and mode are not read from DT by all platforms using this driver, so keep legacy and replace spi_flash_probe_bus_cs() by spi_flash_probe(); - drivers/net/sni_netsec.c : spi speed and mode are not read from DT, so replace spi_flash_probe_bus_cs() by spi_flash_probe(). - drivers/usb/gadget/max3420_udc.c: Can't find any platform which make usage of this driver, nevertheless, keep legacy and replace spi_get_bus_and_cs() by _spi_get_bus_and_cs(). - env/sf.c: a comment indicates that speed and mode are read from DT. So use spi_flash_probe_bus_cs(). Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Marek Behun <marek.behun@nic.cz> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Lukasz Majewski <lukma@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Cc: "Pali Rohár" <pali@kernel.org> Cc: Konstantin Porotchkin <kostap@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Pratyush Yadav <p.yadav@ti.com> Cc: Sean Anderson <seanga2@gmail.com> Cc: Anji J <anji.jagarlmudi@nxp.com> Cc: Biwen Li <biwen.li@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
2022-05-23spi: spi-uclass: Add new spi_get_bus_and_cs() implementationPatrice Chotard
Move legacy spi_get_bus_and_cs() code to _spi_get_bus_and_cs(). Add new spi_get_bus_and_cs() implementation which rely on DT for speed and mode and don't need any drv_name nor dev_name parameters. This will prepare the ground for next patch. Update all callers to use _spi_get_bus_and_cs() to keep the same behavior. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Marek Behun <marek.behun@nic.cz> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Lukasz Majewski <lukma@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Cc: "Pali Rohár" <pali@kernel.org> Cc: Konstantin Porotchkin <kostap@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Pratyush Yadav <p.yadav@ti.com> Cc: Sean Anderson <seanga2@gmail.com> Cc: Anji J <anji.jagarlmudi@nxp.com> Cc: Biwen Li <biwen.li@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
2022-05-23tpm: core: Set timeouts before requesting localityEddie James
Requesting the locality uses the timeout values, so they need to be set beforehand. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-05-23Merge tag 'u-boot-imx-20220523' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20220523 ------------------- CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/12087 Additionally to u-boot-imx20200520: - DH MX8MP - i.MX GPIO: reading GPIO when direction is output - Menlo i.MX53: switch to DM And from u-boot-imx20200520: - fix Verdin hang - add pca9450 regulator - conversion to DM_SERIAL - NAND block handling - fix crypto - enable cache on some boards - add ACC board (MX6)
2022-05-23gpio: rgpio2p: Enhance reading of GPIO pin valueChristoph Fritz
Add support for reading GPIO pin value when function is output. With this patch applied, gpio toggle command is working. Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-05-23clk: sunxi: implement clock driver for suniv f1c100sGeorge Hilliard
The f1c100s has a clock tree similar to those of other sunxi parts. Add support for it. Signed-off-by: George Hilliard <thirtythreeforty@gmail.com> Signed-off-by: Yifan Gu <me@yifangu.com> Acked-by: Sean Anderson <seanga2@gmail.com> [Andre: add PIO and I2C] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-20Merge https://source.denx.de/u-boot/custodians/u-boot-usbTom Rini
generated by cgit v1.2.3 (git 2.0.4) at 2025-11-02 19:35:48 +0000