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This driver provides an interface to access the functions of the system
controller on the Microchip PolarFire SoC.
This driver includes functions to use the system controller to read
the device serial number.
Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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This driver adds support for the single mailbox channel of the MSS
system controller on the Microchip PolarFire SoC.
Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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https://source.denx.de/u-boot/custodians/u-boot-snapdragon
CI: https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/pipelines/27364
Quite a few Smatch issues reported by Andrew, and the LMB allocation
fix.
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The driver specifies 154 pins so should have a maximum selector of 153
to ensure that the index into the array special_pins_names does not
overflow.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Link: https://lore.kernel.org/r/20250807-pinctrl_qcom-v1-2-42fac6707fd5@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
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In sa8775p_get_pin_name the limit check for the index into
msm_special_pins_data allows for more elements than exist. Add code to
ensure the array index remains in bounds.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Link: https://lore.kernel.org/r/20250807-pinctrl_qcom-v1-1-42fac6707fd5@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
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The pointer 'label' is declared and later dereferenced without ever
having a value assigned to it. Add an assignment to this pointer so it
will be valid later when dereferenced.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250723-button-qcom-pmic-v1-1-9c317ac71167@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
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The NULL check for priv in qcom_geni_serial_poll_bit serves no useful
prupose as too much other code surrounding it relies on priv being
valid. Remove the NULL check for priv and other related code.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Link: https://lore.kernel.org/r/20250811-serial_msm_geni-v1-2-4499179491bc@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
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In msm_serial_setbrg if the call to get_clk_div_rate fails then there
will not have been an assignment to clk_div which will lead to the call
to geni_serial_baud using an uninitialised value.
Check for an error from get_clk_div_rate and return an error code if so.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250811-serial_msm_geni-v1-1-4499179491bc@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
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In qcom_snps_eusb2_phy_probe after the call to devm_clk_get if an error
is found then ret is printed but has not been assigned to by the code.
Decode the error from the pointer and assign it to ret.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250806-phy_qcom_snps-v1-1-5cda830026c7@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
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The name of the pin function was changed last minute in the DT, from
emac0 to gmac0.
Adjust the name we use in the pinctrl driver accordingly.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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https://source.denx.de/u-boot/custodians/u-boot-socfpga
This pull request introduces initial U-Boot support for Agilex7 M-series, along
with several enhancements and cleanups across existing Agilex platforms. Key
changes include new board support, DDR driver additions, updated device trees,
and broader SoCFPGA SPL improvements.
Highlights:
- Agilex7 M-series bring-up:
- Basic DT support and board initialization for Agilex7 M-series SoC and
SoCDK.
- New sdram_agilex7m DDR driver with UIBSSM mailbox support and HBM support.
- Clock driver support for Agilex7 M-series.
- New defconfig: socfpga_agilex7m_defconfig.
- Agilex and Agilex5 enhancements:
- Improved SPL support: ASYNC interrupt enabling, system manager init
refactor, and cold scratch register usage.
- Updated firewall probing and watchdog support in SPL.
- Cleaned up DDR code, added secure region support for ATF, and improved warm
reset handling.
- Device Tree and config updates:
- Migration to upstream Linux DT layout for Agilex platforms.
- Consolidated socfpga_agilex_defconfig and removed deprecated configs.
- Platform-specific environment variables for Distro Boot added.
- Driver fixes and cleanups:
- dwc_eth_xgmac and clk-agilex cleanup and improvements.
- Several coverity and style fixes.
Contributions in this PR are from Alif Zakuan Yuslaimi, Tingting Meng, and
Andrew Goodbody. This patch set has been tested on Agilex 5 devkit, Agilex
devkit and Agilex7m devkit.
Passing all pipeline tests at SoCFPGA U-boot custodian
https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27318
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27314
- Several Smatch reported fixes.
- Enable the temperature command on imx8ulp-evk.
- Fix mx8mm_fracpll_tbl.
- Make optee packaging optional for imx8m.
- Reuse and export low_drive_freq_update() on imx9.
- Enable USB OTG ID pin pull up in SPL on dh-imx6.
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Fix wrong memory size calculation in clamshell mode
Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Clean up bit-shift by zero bit
Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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This is for new platform enablement for Agilex7 M-series.
Add DDR driver for Agilex7 M-series. This driver is designed to support
DDR and HBM memory. The official HBM handoff is not ready yet, therefore
hardcoded handoff is used for HBM driver validation on mUDV board.
Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Add uibssm mailbox driver for Agilex7 M-series. HPS will interact with UIB
and HBM subsystem through software defined mailbox interface.
HPS can retrieve HBM memory interface calibration status, UIB
configuration, memory interfae configuration, trigger calibration and etc
with the list of supported mailbox command type and opcode.
Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Agilex7 M-series reuse the clock driver from Agilex.
Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Put all slave CPUs (CPU1-3) into WFI mode. Master CPU (CPU0) writes
the magic word into system manager's scratch register to indicate
the system has performed L2 reset and request reset manager to
perform hardware handshake and then trigger L2 reset. CPU0 put
itself into WFI mode. L2 reset will reboot all HPS CPU cores after
which all HPS cores are in WFI mode. L2 reset is followed by warm
reset request by SPL via RMR_EL3 system register.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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The DDR data rate must be set correctly in the DDRIOCTRL
register according to the Actual Clock Frequency (ACF) value.
By enabling the reading of ACF value from bit 18 of the boot
scratch register during initialization, the DDR data rate is
able to be configured accurately.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Remove redundant code for MPFE CSR firewall disabled as this was
already set in DTreg dts.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Setting up firewall regions based on SDRAM memory banks configuration
(up to CONFIG_NR_DRAM_BANKS banks) instead of using whole address space.
First 1 MiB (0 to 0xfffff) of SDRAM is configured as secure region,
other address spaces are non-secure regions. The ARM Trusted Firmware (ATF)
image is located in this first 1 MiB memory region. So, this can prevent
software executing at non-secure state EL0-EL2 and non-secure masters
access to secure region.
Add common function for firewall setup and reuse for all SoC64 devices.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Replace cm_wait_for_fsm() function with wait_for_bit_le32() function
which supports accurate timeout.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Enable watchdog as early as possible after clock initialization
which is set at 10 seconds.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Update the ARMv8 generic timer frequency register (cntfrq_el0)
with the actual hardware timer frequency (COUNTER_FREQUENCY_REAL).
The generic timer frequency was set to 0x200000000 during boot clk
which needs to be set to 0x400000000 when transition from boot clk
to PLL clk.
This will ensure that subsequent timer operations are based on the
correct frequency, ensuring accurate timekeeping.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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In dwxgmac_of_get_mac_mode there is a test for mac_mode which will
return if false. After this point mac_mode is guaranteed to be true so
there is no need to test for this. Remove that test.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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In xgmac_probe there is a direct return after the point where unwind
gotos start to be used to undo actions performed by earlier code. Use
the appropriate unwind goto instead.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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If the allocation if the bounce buffer fails, virtio_free_pages is called
with a random value from the stack.
Ensure that vring.size is initialized.
Fixes: 37e53db38bdb ("virtio: Allocate bounce buffers for devices with VIRTIO_F_IOMMU_PLATFORM")
Addresses-Coverity-ID: 453314 Uninitialized scalar variable
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
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s25_s28_mdp_ready() returns 1 when spansion_sr_ready() returns negative
value (error code). Fix this problem by following Linux implementation.
Fixes: 1c3dd193b5b ("mtd: spi-nor-core: Add fixups for Cypress s25hl-t/s25hs-t")
Reported-by: Hiroyuki Saito <Hiroyuki.Saito2@infineon.com>
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
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The 'blks' variable in scsi_read/write/erase functions is updated
regardless of pass/fail of the scsi operation . If the scsi operation
fails, 'blkcnt' is updated using an incorrect value of 'blks'. This
wrong 'blkcnt' is returned to the caller and it assumes all blocks were
processed correctly.
Fix this by updating the 'blks' variable only if the scsi operation
succeeds.
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
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In fecmxc_probe if a timeout is detected when resetting the chip no
error code is set before taking the error exit. This could lead to a
silent failure. Instead set an error code.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
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In sc_seco_secvio_dgo_config there is a check for data being NULL but
this occurs after data has already been dereferenced. All callers of the
function provide a valid pointer for data so no need for the NULL check.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
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Add setting default temperatures to the weak version of
get_cpu_temp_grade so these values will not be used uninitialised.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
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For an unknown pll type the error path neglects to free the memory just
allocated. Add the free.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
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Various fixes for smatch warnings, the i2c one might be also coming in
via Heiko / I2C tree, let me know if there is conflict.
There is also W77Q51NW SPI NOR ID support, with the DT portion omitted
for now.
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In rswitch_probe the error detection after the call to devm_clk_get is
very wrong. It checks the value of ret which is uninitialised at that
point. Instead it should be using the macros for including errors into
pointers.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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Add IDs for Winbond W77Q51NW, 512M-bit Secure Serial Flash Memory
with Post-Quantum Cryptography, Dual/Quad SPI, QPI and DTR . The
flash part is similar to W25Q512NWM .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
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In rcar_iic_xfer if nmsgs == 0 the ret will not be assigned to. As ret
will always be 0 if the for loop is entered, may as well just return 0.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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In rcar_clk_set_rate64_div_table the unsigned variable 'value' is used
to receive the return value from rcar_clk_get_table_val which returns an
int and then attempts to test for being less than 0, which can never be
true. Instead declare value as an int so the code can behave as
expected. Also remove initial values from 'value' and 'div' as they are
not needed.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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Add i3c command file to support select, get i3c device
target list, read and write operation.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
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Fix the I3C device with spike filter unable to detect issue by setting
tHIGH_INIT to 200ns for first broadcast address.
This is according to MIPI SPEC 1.1.1 for first broadcast address
which is already part of linux upstreamed patch.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
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Picked linux i3c driver upstraming patch to fix the issue to
probe for i3c controller without slave device attached.
With this fix, the ret check will be on command error and will success
without slave device attached.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
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Add s simple test for the I3C uclass in sandbox.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
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Enable the Kconfig and Makefile for the MIPI DWI3C driver.
hs: fixed typo on drivers/i3c/master/Kconfig
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
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Add new i3c driver to U-Boot drivers.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
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Enable i3c general uclass driver. This uclass driver will have
genaral read and write api to call the specific i3c driver.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
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Enable driver for Synopsis MIPI DWI3C for the family
device agilex5. This driver is migrated from linux version 6.6.37 LTS
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
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In rcar_iic_xfer if nmsgs == 0 the ret will not be assigned to. As ret
will always be 0 if the for loop is entered, may as well just return 0.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
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https://source.denx.de/u-boot/custodians/u-boot-nand-flash
CI: https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/pipelines/27258
This series address issues found by Andrew Goodbody and mostly drop
driver that are not used by any board
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- Pegatron Chagall, Samsung Galaxy R (GT-I9103) and Captivate Glide
(SGH-i927) support
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As no platforms use this driver anymore let's go ahead and remove it.
Signed-off-by: Tom Rini <trini@konsulko.com>
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