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2022-07-07Convert CONFIG_SYS_BOOTCOUNT_LE et al to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SYS_BOOTCOUNT_LE CONFIG_SYS_BOOTCOUNT_BE Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-07arm: Remove PXA architecture supportTom Rini
With the last platform for this architecture removed, remove the rest of the architecture support as well. Cc: Marek Vasut <marex@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-07-07Convert CONFIG_PALMAS_POWER to KconfigTom Rini
This converts the following to Kconfig: CONFIG_PALMAS_POWER Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-07Convert CONFIG_SYS_DISCOVER_PHY to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SYS_DISCOVER_PHY Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-07Convert CONFIG_SYS_UNIFY_CACHE to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SYS_UNIFY_CACHE Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-07usb: ohci-hcd: Remove some unused legacy codeTom Rini
At this point, the only user of ohci-hcd that also uses PCI is using DM, so we can drop CONFIG_PCI_OHCI* usage. No platforms set either of CONFIG_SYS_USB_OHCI_BOARD_INIT or CONFIG_SYS_USB_OHCI_CPU_INIT so those hooks can be removed as well. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-07Convert CONFIG_USB_OHCI_NEW et al to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SYS_OHCI_SWAP_REG_ACCESS CONFIG_SYS_USB_OHCI_CPU_INIT CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS CONFIG_SYS_USB_OHCI_SLOT_NAME CONFIG_USB_ATMEL CONFIG_USB_ATMEL_CLK_SEL_PLLB CONFIG_USB_ATMEL_CLK_SEL_UPLL CONFIG_USB_OHCI_LPC32XX CONFIG_USB_OHCI_NEW Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-07spl: Ensure all SPL symbols in Kconfig have some SPL dependencyTom Rini
Tighten up symbol dependencies in a number of places. Ensure that a SPL specific option has at least a direct dependency on SPL. In places where it's clear that we depend on something more specific, use that dependency instead. This means in a very small number of places we can drop redundant dependencies. Reported-by: Pali Rohár <pali@kernel.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-07Convert CONFIG_USB_XHCI_EXYNOS et al to KconfigTom Rini
This converts the following to Kconfig: CONFIG_USB_XHCI_EXYNOS CONFIG_USB_EHCI_EXYNOS Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-06misc: nuvoton: Add host interface configuration driverJim Liu
add nuvoton BMC npcm750 host configuration driver Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-07-06mmc/aspeed: Enable controller clocksJoel Stanley
Request and enable the controller level clocks. Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06mmc/aspeed: Probe from controllerJoel Stanley
The Aspeed SDHCI controller is arranged with some shared control registers, followed by one or two sets of actual SDHCI registers. Adjust the driver to probe this controller device first. The driver then wants to iterate over the child nodes to probe the SDHCI proper: ofnode node; dev_for_each_subnode(node, parent) { struct udevice *dev; int ret; ret = device_bind_driver_to_node(parent, "aspeed_sdhci", ofnode_get_name(node), node, &dev); if (ret) return ret; } However if we did this the sdhci driver would probe twice; once "naturally" from the device tree and a second time due to this code. Instead of doing this we can rely on the probe order, where the controller will be set up before the sdhci devices. A better solution is preferred. Select MISC as the controller driver is implemented as a misc device. Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06mmc/aspeed: Add debuging for clock probe failuresJoel Stanley
Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06clk/ast2500: Add SD clockJoel Stanley
In order to use the clock from the sdhci driver, add the SD clock. Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06clk/ast2600: Adjust eMMC clock namesJoel Stanley
Adjust clock to stay compatible with those used by the Linux kernel device tree. Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06clk/aspeed: Add debug message when clock failsJoel Stanley
A common message across platforms that prints the clock number. Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06i2c/aspeed: Add AST2600 compatibleJoel Stanley
Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-07-06i2c/aspeed: Fix reset controlJoel Stanley
The reset control was written for the ast2500 and directly programs the clocking register. So we can share the code with other SoC generations use the reset device to deassert the I2C reset line. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-07-06reset/aspeed: Implement status callbackJoel Stanley
The I2C driver shares a reset line between buses, so allow it to test the state of the reset line before resetting it. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-07-06soc: soc_ti_k3: identify j7200 SR2.0 SoCsBryan Brattlof
Anytime a new revision of a chip is produced, Texas Instruments will increment the 4 bit VARIANT section of the CTRLMMR_WKUP_JTAGID register by one. Typically this will be decoded as SR1.0 -> SR2.0 ... however a few TI SoCs do not follow this convention. Rather than defining a revision string array for each SoC, use a default revision string array for all TI SoCs that continue to follow the typical 1.0 -> 2.0 revision scheme. Signed-off-by: Bryan Brattlof <bb@ti.com>
2022-07-06phy: nuvoton: add NPCM7xx phy control driverJim Liu
add BMC NPCM750 phy control driver Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-07-06firmware: ti_sci_static_data: Make file board agnosticVignesh Raghavendra
Static DMA channel data for R5 SPL is mostly board agnostic so use SOC configs instead of EVM specific config to ease adding new board support. Drop J7200 EVM specific settings as its same as J721e Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com>
2022-07-05Convert CONFIG_SYS_FSL_PCI_VER_3_X to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SYS_FSL_PCI_VER_3_X Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05Convert CONFIG_PCI_MSC01 to KconfigTom Rini
This converts the following to Kconfig: CONFIG_PCI_MSC01 Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05Convert CONFIG_SH7751_PCI to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SH7751_PCI Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05Convert CONFIG_PCI_CONFIG_HOST_BRIDGE to KconfigTom Rini
This converts the following to Kconfig: CONFIG_PCI_CONFIG_HOST_BRIDGE Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05Convert CONFIG_PCI_GT64120 to KconfigTom Rini
This converts the following to Kconfig: CONFIG_PCI_GT64120 Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05Convert CONFIG_PCI_SCAN_SHOW to KconfigTom Rini
This converts the following to Kconfig: CONFIG_PCI_SCAN_SHOW Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05pci: Remove pci_sh4 and related defines.Tom Rini
This driver is not enabled anywhere, remove it. Also remove definitions of symbols only used in this driver, on platforms that did not enable it. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05Convert CONFIG_PCIE_IMX to KconfigTom Rini
This converts the following to Kconfig: CONFIG_PCIE_IMX Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05Convert CONFIG_SYS_FSL_SEC_MON et al to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SYS_FSL_SEC_MON CONFIG_SYS_FSL_SEC_MON_BE CONFIG_SYS_FSL_SEC_MON_LE Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05Convert CONFIG_ESDHC_DETECT_QUIRK to KconfigTom Rini
This converts the following to Kconfig: CONFIG_ESDHC_DETECT_QUIRK Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05Convert CONFIG_SYS_DDR_RAW_TIMING to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SYS_DDR_RAW_TIMING Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05Convert CONFIG_SYS_SPD_BUS_NUM to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SYS_SPD_BUS_NUM Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05Convert CONFIG_USB_GADGET_DWC2_OTG_PHY to KconfigTom Rini
This converts the following to Kconfig: CONFIG_USB_GADGET_DWC2_OTG_PHY Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05Convert CONFIG_SAMSUNG_ONENAND to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SAMSUNG_ONENAND Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-07-05Rename CONFIG_PWM to CONFIG_PWM_S5P and move to KconfigTom Rini
We rename the S5P specific "CONFIG_PWM" to CONFIG_PWM_S5P and move it to Kconfig. Given the usage of CONFIG_PWM_NX, we have that select this new symbol. Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-07-05nxp: Cleanup some emulator related options.Tom Rini
- Drop the emulator CONFIG test from include/configs/ls1088ardb.h - Migrate CONFIG_SYS_FSL_DDR_EMU to a select'able option in drivers/ddr/fsl/Kconfig Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05watchdog: designware: Make this depend on WDTTom Rini
As this driver can dynamically determine the values set in CONFIG_DW_WDT_BASE when using WDT, so make this depend on WDT rather than migrate CONFIG_DW_WDT_BASE to Kconfig. Cc: Chee Tien Fong <tien.fong.chee@intel.com> Cc: Chin-Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinh.nguyen@intel.com> Cc: Holger Brunck <holger.brunck@hitachienergy.com> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Marek Vasut <marex@denx.de> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com> Cc: Stefan Roese <sr@denx.de> Cc: hee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefan Roese <sr@denx.de>
2022-07-05net: designware: Rename CONFIG_DW_GMAC_DEFAULT_DMA_PBL to GMAC_DEFAULT_DMA_PBLTom Rini
This value is always used at the default, rename it for now. This likely should come from the device tree if non-default, moving forward. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05Convert CONFIG_DW_ALTDESCRIPTOR to KconfigTom Rini
This converts the following to Kconfig: CONFIG_DW_ALTDESCRIPTOR Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-03mtd: rawnand: fsl_elbc: Fix detection when nand_scan_ident() has not ↵Pali Rohár
selected ecc.mode ecc.mode is set to 0 (aliased to NAND_ECC_NONE) either when function nand_scan_ident() has not selected ecc.mode or when it selected it to none ecc mode. Distinguish between these two states by checking of node property "nand-ecc-mode" which function nand_scan_ident() uses for filling ecc.mode. This change fixes usage of none ecc mode if it is specified in DTS file. Fixes: c9ea9019c5aa ("mtd: rawnand: fsl_elbc: Use ECC configuration from device tree") Signed-off-by: Pali Rohár <pali@kernel.org>
2022-06-30Merge tag 'u-boot-at91-2022.10-a' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-at91 into next First set of u-boot-at91 features for the 2022.10 cycle: This feature set includes mostly fixes and alignments: DT alignment with Linux for sama7g5, removal of invalid eeprom compatibles, removal of extra debug_uart_init calls for all at91 boards, support for pio4 driver pioE bank, and other minor fixes and enhancements for sam9x60 and sama5d2_icp boards.
2022-06-30Merge tag 'versal-qspi-for-v2022.10' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next Versal QSPI/OSPI changes for v2022.10 - Add new flash types - Add cadence ospi driver for Xilinx Versal
2022-06-30gpio: atmel_pio4: add support for PIO_PORTEMihai Sain
Add support for gpio PORT E, which is available on e.g. sama7g5 SoC. Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
2022-06-29spi: cadence-qspi: Fix programming ospi flash speedT Karthik Reddy
When the requested flash speed is 0, the baudrate division for the requested speed causing drop in the performance. So set the ospi flash to operate at max frequency when requested speed is zero. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220512100535.16364-6-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-29spi: cadence_qspi: Enable apb linear mode for apb read & write operationsT Karthik Reddy
On versal platform, enable apb linear mode for apb read and write execute operations amd disable it when using dma reads. This is done by xilinx_pm_request() secure calls when CONFIG_ZYNQMP_FIRMWARE is enabled, else we use direct raw reads and writes in case of mini U-Boot. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220512100535.16364-5-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-29spi: cadence-qspi: reset qspi flash for versal platformT Karthik Reddy
When flash operated at non default mode like DDR, flash need to be reset to operate in SDR mode to read flash ids by spi-nor framework. Reset the flash to the default state before using the flash. This reset is handled by a gpio driver, in case of mini U-Boot as gpio driver is disabled, we do raw read and write access by the registers. Versal platform utilizes spi calibration for read delay programming, so incase by default read delay property is set in DT. We make sure not to use read delay from DT by overwriting read_delay with -1. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220512100535.16364-4-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-29arm64: versal: Add versal specific cadence ospi driverT Karthik Reddy
Add support for cadence ospi driver for Versal platform. This driver provides support for DMA read operation which utilizes cadence qspi driver. If "cdns,is-dma" DT property is specified use dma for read operation from cadence_qspi driver. As cadence_qspi_apb_dma_read() is defined in cadence_ospi_versal driver add a weak function defination in cadence_qspi driver. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220512100535.16364-3-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-29spi: cadence-qspi: move cadence qspi macros to header fileT Karthik Reddy
Move all the cadence macros from cadence_qspi_apb.c to cadence_qspi.h file. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220512100535.16364-2-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
generated by cgit v1.2.3 (git 2.0.4) at 2025-11-02 19:35:27 +0000