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Vasileios Amoiridis <vassilisamir@gmail.com> says:
This patch adds support to save the bootcount variable in a file located in
FAT filesystem. Up to now, there was support only for EXT filesystem.
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Add support to save boot count variable in ANY filesystem. Tested with
FAT and EXT.
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Philip Oberfichtner <pro@denx.de>
Signed-off-by: Vasileios Amoiridis <vasileios.amoiridis@cern.ch>
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On some SoCs, like Qualcomm SoCs, the PSCI cluster power domain
is used by system-wide firmware interfaces to make sure none
of the CPUs are suspended before submitting requests.
While on U-boot we only use the first core and we never
suspend it, the Device Tree still references it and blocks
those nodes to be probed.
Simply bind the PSCI power-domain subnoded to a stub power
domain driver in order to solve the runtime dependencies.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
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Nothing really major here, some rework of the SPL PMIC drivers, adding
support for the AXP717 on the way, which is showing up on newer boards
now, most prominently some Anbernic handheld gaming devices. The rest
is enabling Ethernet and SPI boot on the Allwinner V3s SoC, plus two
fixes. This also updates the "traditional U-Boot" DTs to that of kernel
v6.9. I will look into upgrading some SoCs to dts/upstream in the
coming cycle, though this will not cover all SoCs for now, as we carry
some non-mainline fix to improve compatibility with older kernels. Will
see how it goes, but for now we stick with the "old way".
The branch survived the gitlab CI run, and Linux boot testing on some
selected boards.
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The driver is trying to read the "spi-max-frequency" property of the
*controller* driver node. There is no such property. The
"spi-max-frequency" property belongs to the SPI devices on the bus.
Right now, the driver will always fall back to the default value of 1MHz
and thus flash reads are very slow with just about 215kb/s.
In fact, the SPI uclass will already take care of everything and we just
have to clamp the frequency to the values the driver/hardware supports.
Thus, drop the whole max_hz handling.
Signed-off-by: Michael Walle <mwalle@kernel.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Andre Przywara <andre.przywara@arm.com>
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Add the compatible string for the emac found on the V3s SoC. The SoC
only supports the internal PHY. There are no (R)MII signals on any pins.
Signed-off-by: Michael Walle <mwalle@kernel.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
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Add the clock gate registers as well as the reset register bits for the
EMAC and EPHY for the V3s. These are needed by the sun8i network driver.
Signed-off-by: Michael Walle <mwalle@kernel.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
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The generic AXP SPL driver implementation can cover all regulators we
need for the AXP305.
Add the descriptions for four of the six DC/DC regulators of the AXP305,
and enable that when CONFIG_AXP305_POWER is enabled. We won't need DCDC2
and DCDC3, but by using the position in the array for the index we keep
the code cleaner.
Also remove the old driver, and switch the Makefile to include the new,
generic driver.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The generic AXP SPL driver implementation can cover all regulators we
need for the AXP313.
Add the descriptions for the three DC/DC regulators of the AXP313, and
enable that when CONFIG_AXP313_POWER is enabled. Also remove the old
driver, and switch the Makefile to include the new, generic version.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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On boards using the AXP717 PMIC, the DRAM rail is often not setup
correctly at reset time, so we have to program the PMIC very early in
the SPL, before running the DRAM initialisation.
Using the new generic AXP SPL driver, add the Kconfig options and
platform bits needed to support an AXP717 PMIC chip in I2C mode.
This allows to set up the correct voltage for the DRAM chips and the
CPU cores.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Ryan Walklin <ryan@testtoast.com>
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So far we had a separate driver file for each AXP PMIC chip that we need
to support in the SPL. The code in there was largely similar, but
differed in many details.
Based on the idea of the DM AXP driver, introduce a data structure to
describe each regulator in a compact way. This is a simplified version
of the struct used in the DM driver, as we don't need to support the full
voltage range and not every regulator in the SPL.
For now we only support the DC/DC buck converters, since that's what we
need the SPL to configure, mostly. Also we get rid of the regulator name,
and hardcode the regulator number by its position in the array (first is
DCDC1, second is DCDC2, etc). We also drop support for the value table,
we ideally won't need that for the subset of regulators required.
At the end each regulator is described by a 10 bytes struct, so we avoid
blowing up the SPL footprint, but still can use generic code.
Each chip is supposed to be described separately, and protected by
ifdef's, to only build in the regulators needed for a particular board.
We also describe the bits to help identifying the AXP chip, and the
shutdown details in that section.
Add a generic driver, that exports axp_set_dcdc<x>() functions to set up
the buck converters. For now this just contains the bits for the (new)
AXP717, but it's not wired up anywhere yet.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The axp<xxx>.c drivers are only used for the SPL, for U-Boot proper we
have a separate, DM compliant driver.
Mask the build instructions with CONFIG_SPL_BUILD, to avoid them being
build for U-Boot proper as well.
The AXP221 driver defines axp_get_sid(), which is used in the U-Boot
proper cpuinfo() code, and some old LCD code directly calls axp_set_eldo(),
so we keep that driver outside the new guards. This will be fixed properly
later.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2024-10-rc1-2
Documentation:
* use current versions of certifi and urllib3 for building documentation
* add bootelf command documentation
* correct the description of the Goldfish RTC driver
* correct heading level of itest examples
UEFI:
* print device-tree in dtbdump.efi
* consider CONFIG_EFI_IGNORE_OSINDICATIONS in TestEfiCapsuleFirmwareRaw
* correct cmd_capsule_esl_gen invocation in scripts/Makefile.lib
* use capsule CRT instead of ESL file when building capsules
Others:
* let ENV_IS_IN_EXT4 enable SYS_MMC_ENV_DEV
* check if CONFIG_SYS_MMC_ENV_DEV is defined in mmc_get_env_dev
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The X-Powers AXP717 is a PMIC with four buck converters and a number
of LDOs, one of which is actually fixed (so not modelled here).
Add the compatible string and the respective regulator ranges to allow
drivers to adjust voltages.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Ryan Walklin <ryan@testtoast.com>
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Replace the incorrect description that was copied from another driver.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
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In some cases (consistently in my case with an embedded board) the
ethernet controller will time out on the first init but always succeed
after reset.
Let's reset the controller during probe so we always start with it in a
known state, and don't have wait for the first asix_wait_link() to
time out.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
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https://source.denx.de/u-boot/custodians/u-boot-dfu
u-boot-dfu-20240711
Usb gadget:
- A welcome cleanup: epautoconf workaround is dropped to use
.match_ep() instead
- Introduce handle_interrupts() op for USB_GADGET_GENERIC, which
allows a per-driver interrupt handling
Fastboot:
- Fix mssing include when building with TCP only
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The ARASAN MMC controller on Keystone 3 class of devices need the SDCD
line to be connected for proper functioning.
In cases where this can't be connected, add a quirk to force the
controller into test mode and set the TESTCD bit. Use the flag
"ti,fails-without-test-cd", to implement this above quirk when required.
Additionally, this quirk also avoids waiting for the controller debounce
time.
This commit is similar to linux kernel commit c7666240ec76
("drivers: mmc: sdhci_am654: Add the quirk to set TESTCD bit").
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
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Christian Marangi <ansuelsmth@gmail.com> says:
This is an initial series that have all the initial trivial
fixes required for usage of OF_UPSTREAM for the mediatek SoC
This also contains the pcie-gen3 driver and the required tphy
support driver to make it work.
Subsequent series will follow with conversion of the mtk-clk
to permit usage of OF_UPSTREAM and upstream clk ID.
MT7981, MT7986 and MT7988 migration to upstream clock ID
is complete and working on MT7623.
Series CI tested with PR: https://github.com/u-boot/u-boot/pull/590
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Support alternative compatible for fixed-plls clocks used upstream with
the compatible mediatek,mt7986-apmixedsys.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Support alternative compatible for fixed-plls clocks used upstream with
the compatible mediatek,mt7988-apmixedsys.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Set pcie-phy optional for PCIe gen3. MT7988 doesn't require it and
making it mandatory prevent the driver to correctly probe.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Upstream kernel linux define pinctrl for uart0, hence this pin group
and pinctrl driver is needed before relocation. Add DM_FLAG_PRE_RELOC
flag to init and mute mtk_serial error on early serial init.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Add support for gpio-controller property in root pinctrl node.
This is to follow upstream linux DTSI that doesn't define the
gpio-controller and cells in dedicated nodes.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Support alternative compatible for fixed-plls clocks used upstream with
the compatible mediatek,mt7981-apmixedsys.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Add support for upstream linux clock and map U-Boot property to the one
use in upstream linux where supported.
Also add handling for the use_internal_cd that on upstream is hardcoded
enabled on mt7620.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Upstream linux serial driver use a different logic to setup serial regs.
They have 2 interval:
- < 115200 we use lowspeed regs and 16 * baud
- >= 115200 we use highspeed
We currently use force_highspeed property to force usage of highspeed
regs even with low baud rate.
Add special handling if the upstream compatible is used where we just
apply the same interval with anything >= 115200 in highspeed simulating
force_highspeed.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Upstream linux also provide the additional optional bus clock.
Add support for it and also enable the baud and bus clock on probe.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Add support for optional arb and pmic clock for i2c provided in upstream
linux DTSI.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
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Handle alternative name for pn_swap property as upstream linux use
mediatek,pnswap.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Upstream kernel linux use a different compatible mediatek,spi-ipm.
Add support for this compatible and add handling for the additional
clock similar to how it's done by the upstream driver and handling for
all the property enabled by default.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Add MediaTek GEN3 PCIe controller support for filogic silicon.
This is adapted from the Linux version of the driver.
Signed-off-by: John Crispin <john@phrozen.org>
[ fix minor problems, fix checkpatch errors ]
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Add support for PHY type switch via the mediatek topmisc syscon.
This is needed on mt7981 to make the PCIe correctly work and display
LinkUp.
Follow the same implementation done on Linux kernel with the usage of
the mediatek,syscon-type property.
Example:
u3port0: usb-phy@11e10700 {
reg = <0x11e10700 0x900>;
clocks = <&topckgen CK_TOP_USB3_PHY_SEL>;
clock-names = "ref";
#phy-cells = <1>;
mediatek,syscon-type = <&topmisc 0x218 0>;
status = "okay";
};
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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- Add mvebu_espressobin_ultra-88f3720_defconfig (Benjamin)
- Update DTS for Thecus N2350 board (Tony)
- Add "old" Marvell DDR3 training for Armada 38x and Turris Omnia
(Marek)
- Misc turris_omnia changes (Marek)
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/21504
- Fixes for i.MX8M and i.MX93 clk-composite.
- Set CAN oscillator frequency based on model on verdin-imx8mm.
- Enable CAAM for phycore-imx8mp_defconfig.
- Miscellaneous improvements for Gateworks i.MX8M boards.
- Fix initramfs boot on msc_sm2s_imx8mp.
- Fixe EQoS on imx8mp-beacon-kit.
- Fix error message in fsl_esdhc_imx.
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https://source.denx.de/u-boot/custodians/u-boot-sh
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Add optional support for using old DDR3 training code from 2017.
The code lives in drivers/ddr/marvell/a38x/old/. To prevent symbol
clashing with new DDR3 training code, a special header which renames all
clashing symbols via macros is included and the symbols are prefixed
with 'old_'.
If old DDR3 training support is selected for a board, then the SPL
initialization code calls a new function
board_use_old_ddr3_training()
to check whether it should use old DDR3 training code. The default
weak implementation returns false, defaulting to new DDR3 training code.
Boards that wish to support this need to select the
ARMADA_38X_SUPPORT_OLD_DDR3_TRAINING
config option and implement the old version of DDR topology provider,
ddr3_get_topology_map().
Signed-off-by: Marek Behún <kabel@kernel.org>
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Backport the option to compile with immutable debug settings also to
the old implementation of the DDR3 training code.
The original PR for mv-ddr-marvell can be seen at
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/45/
Signed-off-by: Marek Behún <kabel@kernel.org>
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Fix some compilation warning in the old DDR training code.
Signed-off-by: Marek Behún <kabel@kernel.org>
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Import DDR training code from commit 1b69ce2fc0ec ("arm: mvebu:
ddr3_debug: remove self assignments") into
drivers/ddr/marvell/a38x/old/. The code is not used yet.
Explanation:
Since 2019, on some Turris Omnia boards we have been having problems
with newer versions of Marvell's DDR3 training code for Armada 38x,
which is ported from mv-ddr-marvell [1] to U-Boot into the
drivers/ddr/marvell/a38x/ directory:
- sometimes the DDR3 training fails on some older boards, sometime it
fails on some newer boards
- other times it succeeds, but some boards experience crashes of the
operating system after running for some time.
Using the stock version of Turris Omnia's U-Boot from solved these
issues, but this solution was not satisfactory, since we wanted
features from new U-Boot.
Back in 2020-2022 we have spent several months trying to debug the
issues, working with Marvell, on our own, and also with U-Boot
community, but these issues persist still.
One solution we used back in 2019 was a "hybrid U-Boot": the SPL part
(containing the DDR3 training code) was taken from the stock version,
while the proper part was current U-Boot at the time. This solution also
has its drawbacks, of which the main one is the need to glue binaries
from two separate builds.
Since then there have been some more changes to the DDR3 training code
in upstream mv-ddr-marvell that have been ported to U-Boot. We have
provided our users experimental builds of U-Boot in the TurrisOS so that
they could try upgrading the firmware and let us know if those problems
still exist. And they do.
We do not have the time nor manpower to debug this problem and fix it
properly. Marvell was also no able to provide a solution to this,
probably because they do not have the manpower as well.
I have therefore come up with this "not that pretty" solution: take the
DDR3 training code from an older version of U-Boot that is known to
work, put it into current U-Boot under old/ subdirectory within
drivers/ddr/marvell/a38x/, build into the SPL binary both the old and
new versions and make it possible to select the old version via an env
variable.
[1] https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell
Signed-off-by: Marek Behún <kabel@kernel.org>
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reduce binary size
Allow compiling with immutable debug settings:
- DEBUG_LEVEL is always set to DEBUG_LEVEL_ERROR
- register dumps are disabled
This can save around 10 KiB of space in the resulting binary, which is a
lot in U-Boot SPL.
Signed-off-by: Marek Behún <kabel@kernel.org>
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and make them static
The variables is_validate_window_per_if, is_validate_window_per_pup,
sweep_cnt and is_run_leveling_sweep_tests are only used if
DDR_VIEWER_TOOL macro is defined, so define them only in that case.
Make them static since they are only used in ddr3_debug.c.
Signed-off-by: Marek Behún <kabel@kernel.org>
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The variables is_default_centralization, is_tune_result and
is_bist_reset_bit are never used.
Signed-off-by: Marek Behún <kabel@kernel.org>
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won't print anything
Return from ddr3_tip_print_log() early if we won't print anything
anyway.
This way the compiler can optimize away the VALIDATE_IF_ACTIVE() calls
in the for-loop, so if the SILENT_LIB macro is defined, no code is
generated for the rest of the function, which saves some space.
Signed-off-by: Marek Behún <kabel@kernel.org>
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Upstream Linux commit f90b68d6c8b0.
The CORE/BUS root slice has following design, simplied graph:
The difference is core not have pre_div block.
A composite core/bus clk has 8 inputs for mux to select, saying clk[0-7].
It support target(smart) interface and normal interface. Target interface
is exported for programmer easy to configure ccm root. Normal interface
is also exported, but we not use it in our driver, because it will
introduce more complexity compared with target interface.
The normal interface simplified as below:
SEL_A GA
+--+ +-+
| +->+ +------+
CLK[0-7]--->+ | +-+ |
| | | +----v---+ +----+
| +--+ |pre_diva+----> | +---------+
| +--------+ |mux +--+post_div |
| +--+ |pre_divb+--->+ | +---------+
| | | +----^---+ +----+
+--->+ | +-+ |
| +->+ +------+
+--+ +-+
SEL_B GB
The mux in the upper pic is not the target interface MUX, target
interface MUX is hiding SEL_A and SEL_B. When you choose clk[0-7],
you are actually writing SEL_A or SEL_B depends on the internal
counter which will also control the internal "mux".
The target interface simplified as below which is used by Linux Kernel:
CLK[0-7]--->MUX-->Gate-->pre_div-->post_div
A requirement of the Target Interface's software is that the
target clock source is active, it means when setting SEL_A, the
current input clk to SEL_A must be active, same to SEL_B.
We touch target interface, but hardware logic actually also need
configure normal interface.
There will be system hang, when doing the following steps:
The initial state:
SEL_A/SEL_B are both sourcing from clk0, the internal counter
choose SEL_A.
1. switch mux from clk0 to clk1
The hardware logic will choose SEL_B and configure SEL_B to clk1.
SEL_A no changed.
2. gate off clk0
Disable clk0, then the input to SEL_A is off.
3. switch from clk1 to clk2
The hardware logic will choose SEL_A and configure SEL_A to clk2,
however the current SEL_A input clk0 is off, the system hang.
The solution to fix the issue is in step 1, write twice to
target interface MUX, it will make SEL_A/SEL_B both sources
from clk1, then no need to care about the state of clk0. And
finally system performs well.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
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Make public the clk_fetch_parent_index and rename it. This allow
us to be reused in driver specialization
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
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Add missing newline character and also add the return code of
regulator_set_value() to the output.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
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Synchronize R-Car R8A779G0 V4H PFC tables with Linux 6.9.3,
commit 1b4861e32e461b6fae14dc49ed0f1c7f20af5146 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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Synchronize R-Car R8A779H0 V4M clock tables with Linux 6.9.3,
commit 1b4861e32e461b6fae14dc49ed0f1c7f20af5146 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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