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2023-03-02sandbox: Tidy up RTC optionsSimon Glass
At present we enable the sandbox RTC driver for all builds. Add a separate Kconfig option to control this, so that it can be disabled in TPL, where it is not needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-02Correct SPL uses of PHY_FIXEDSimon Glass
This converts 3 usages of this option to the non-SPL form, since there is no SPL_PHY_FIXED defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-02Correct SPL uses of MULTIPLEXERSimon Glass
This converts 3 usages of this option to the non-SPL form, since there is no SPL_MULTIPLEXER defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-03-02Correct SPL uses of DISPLAY_AER_FULLSimon Glass
This converts 2 usages of this option to the non-SPL form, since there is no SPL_DISPLAY_AER_FULL defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-02sh4: Drop unused twl6030 driverSimon Glass
This is not used. Drop the driver and Kconfig option. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-02mtd: Drop unused kb9202_nand driverSimon Glass
This is not used since time out of mind. Drop the driver and Kconfig option. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Michael Trimarchi <michael@amarulasolutions.com>
2023-03-02usb: xhci-mtk: modify the SOF/ITP interval for mt8195Chunfeng Yun
There are 4 USB controllers on MT8195, the controllers (IP1~IP3, exclude IP0) have a wrong default SOF/ITP interval which is calculated from the frame counter clock 24Mhz by default, but in fact, the frame counter clock is 48Mhz, so we shall set the accurate interval according to 48Mhz for those controllers. Note: The first controller no need set it, but if set it, shall change tphy's pll at the same time. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Marek Vasut <marex@denx.de>
2023-03-02phy: phy-mtk-tphy: add support mt8195Chunfeng Yun
The T-PHY controller is designed to use use PLL integer mode, but in fact use fractional mode for some ones on mt8195 by mistake, this causes signal degradation (e.g. eye diagram test fail), fix it by switching PLL to 26Mhz from default 48Mhz to improve signal quality. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
2023-03-02phy: phy-mtk-tphy: remove macros to prepare bitfield valueChunfeng Yun
Prefer to make use of FIELD_PREP() macro to prepare bitfield value, then no need local macros anymore. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
2023-03-02usb: dwc3-meson-g12a: Select PHY instead of imply PHYMarek Vasut
Imply means you can turn off the option and expect things to work - "it's a good idea to have X enabled" is when to use imply - "you must have X for Y to work" is when to use select Use "select" here. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2023-03-01sandbox: fix building with CONFIG_SPL_TIMER=yHeinrich Schuchardt
Building sandbox_defconfig with CONFIG_SPL_TIMER=y results in an error include/dm/platdata.h:63:33: error: static assertion failed: "Cannot use U_BOOT_DRVINFO with of-platdata. Please use devicetree instead" Add a missing condition in the sandbox driver. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-01arm64: a37xx: pinctrl: probe after bindingRobert Marko
Currently, pinctrl drivers are getting probed during post-bind, however that is being reverted, and on A37XX pinctrl driver is the one that registers the GPIO driver during the probe. So, if the pinctrl driver doesn't get probed GPIO-s won't get registered and thus they cannot be used. This is a problem on the Methode eDPU as it just uses SB pins as GPIO-s and without them being registered networking won't work as it only has one SFP slot and the TX disable GPIO is on the SB controller. So, lets just add a flag only to A37XX driver to probe after binding in order for the GPIO driver to always get registered. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-01arm: mvebu: Add support for generating NAND kwbimagePali Rohár
Add a new Kconfig option CONFIG_MVEBU_SPL_BOOT_DEVICE_NAND which instruct make to generate kwbimage with NAND header. This image is used for booting from NAND flash (either SPI or parallel). Support is very simple, SPL after finishes DDR training returns back to the BootROM (via CONFIG_SPL_BOOTROM_SUPPORT option) and BootROM then loads and executes U-Boot proper. To generate correct kwbimage NAND header, it is required to set following Kconfig options: CONFIG_SYS_NAND_PAGE_SIZE CONFIG_SYS_NAND_BLOCK_SIZE CONFIG_MVEBU_SPL_NAND_BADBLK_LOCATION They are used only by make / mkimage when generating final kwbimage. CONFIG_MVEBU_SPL_NAND_BADBLK_LOCATION is a new mvebu specific Kconfig option which is set into kwbimage NAND_BADBLK_LOCATION header field. Signed-off-by: Pali Rohár <pali@kernel.org>
2023-02-28Merge tag 'tpm-next-28022023' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-tpm into next TPM auto startup and testing: Due to U-Boot's lazy binding we always relied on command line tools to initialize the TPM subsystem and devices. One exception is the EFI subsystem. When compiled with TCG2 measured boot support the TPM was automatically initialized. However that init was not complete. The TCG specs [0] (and specifically §12.3 Self-test modes) describe how self-tests on the device should be performed. This PR is adding an extra API function, that can be used to initialize the TPM2.0 properly. Simon added the equivalent for TPM1.2 and refactored the DM tests to include the new funtion. [0] https://trustedcomputinggroup.org/wp-content/uploads/TPM-Rev-2.0-Part-1-Architecture-01.07-2014-03-13.pdf
2023-02-28Merge tag 'u-boot-nand-20230227' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-nand-flash into next Pull request for u-boot-nand-20230227 - mark reserved blocks from Ashok Reddy Soma - backport BRCMNAND changes from Linux from Linus Walleij - fix display of unknown raw ID from Patrice Chotard - show reserved block in chip.erase from Michael Trimarchi
2023-02-28clk: rockchip: rk3568: add more supported clk rates for sdmmc and emmcVasily Khoruzhick
SDHCI driver may attempt to set 26MHz clock, but clk_rk3568 will return error in this case. Apparently, SDHCI silently ignores the error and as a result eMMC initialization fails. Add 25 MHz and 26 MHz clk rates for sdmmc and emmc on rk3568 to fix that. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: efuse: Add support for RK3036Jonas Karlman
Add support for rk3036 compatible. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: efuse: Add support for RK3128Jonas Karlman
Add support for rk3128 compatible. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: efuse: Add support for RK3328Jonas Karlman
Add support for rk3328 compatible. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: efuse: Add support for RK3288 and moreJonas Karlman
Add support for rk3066a, rk3188, rk322x and rk3288 compatible. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: efuse: Refactor to use driver data and opsJonas Karlman
Refactor the driver to use driver data and ops to simplify handling of SoCs that require a unique read op. Move handling of the aligned bounce buffer to main read op in order to keep the SoC unique read op simple. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: otp: Add dump_otp debug commandJonas Karlman
Add a simple debug command to dump the content of the otp. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: otp: Add support for RK3588Jonas Karlman
Add support for rk3588 compatible. Adjust offset using driver data in main read op. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: otp: Add support for RK3568Jonas Karlman
Add support for rk3568 compatible. Handle allocation of an aligned bounce buffer in main read op in order to keep the SoC unique read op simple. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: otp: Refactor to use driver data and opsJonas Karlman
Refactor the driver to use driver data and ops to simplify handling of SoCs that require a unique read op. Use readl_poll_sleep_timeout instead of a custom poll loop, and add validation of input parameter to main read op. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28ram: rockchip: Add rk3588 ddr driver supportJagan Teki
Add ddr driver for rk3588 to get the ram capacity. Co-developed-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28clk: rockchip: pll: Add pll_rk3588 type for rk3588Jagan Teki
Add RK3588 pll set and get rate clock support. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28clk: rockchip: Add rk3588 clk supportJagan Teki
Add clock driver support for Rockchip RK3588 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28gpio: gpio-rockchip: parse gpio-ranges for bank idChris Morgan
Use the new devicetree property of gpio-ranges to determine the GPIO bank ID. Preserve the "old" way of doing things too, so that boards can be migrated and tested gradually (I only have a 3566 and 3326 to test). Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: rk3568: add rk3568 pinctrl driverJagan Teki
Add driver supporting pin multiplexing on rk3568 platform. Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Co-developed-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28drivers: phy: add naneng combphy for rk3568Jagan Teki
RK3568 has three combo phys, and PCIe/USB3/SATA/QSGMII controllers share one pipe interface for each combo phy, here is the diagram of the complex connection. +----------------+ | | +------+ | USB3 OTG CTRL0 |---->| | | | | | +------------+ +----------------+ | PIPE | | | | MUX |---->| Combo PHY0 | +----------------+ | | | | | | | | +------------+ | SATA CTRL0 |---->| | | | +------+ +----------------+ +----------------+ | | +------+ | USB3 HOST CTRL1|---->| | | | | | +------------+ +----------------+ | PIPE | | | | MUX |---->| Combo PHY1 | +----------------+ | | | | | |---->| | +------------+ | SATA CTRL1 | -->| | | | | +------+ +----------------+ | | +----------------+ | | | | +------+ | QSGMII CTRL |---->| | | | | | +------------+ +----------------+ | PIPE | | | | MUX |---->| Combo PHY2 | +----------------+ | | | | | |---->| | +------------+ | SATA CTRL2 | -->| | | | | +------+ +----------------+ | | +----------------+ | | | | | PCIe2 1-Lane |--- | | +----------------+ Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Co-developed-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28phy: rockchip-inno-usb2: Add USB2 PHY for rk3568Manoj Sai
RK3568 has two USB 2.0 PHYs, and each PHY has two ports, the OTG port of PHY0 support OTG mode with charging detection function, they are similar to previous Rockchip SoCs. However, there are three different designs for RK3568 USB 2.0 PHY. 1. RK3568 uses independent USB GRF module for each USB 2.0 PHY. 2. RK3568 accesses the registers of USB 2.0 PHY IP directly by APB. 3. The two ports of USB 2.0 PHY share one interrupt. This patch only PHY1 with necessary attributes required to function USBPHY1 on U-Boot. Co-developed-by: Ren Jianing <jianing.ren@rock-chips.com> Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com> Co-developed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28phy: rockchip: inno-usb2: Add support #address_cells = 2Jagan Teki
New Rockchip devices have the usb phy nodes as standalone devices. These nodes have register nodes with #address_cells = 2, but only use 32 bit addresses. Adjust the driver to check if the returned address is "0", and adjust the index in that case. Derived and adjusted the similar change from linux-next with below commit <9c19c531dc98> ("phy: phy-rockchip-inno-usb2: support #address_cells = 2") Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28mmc: rockchip_dw_mmc: fix DDR52 8-bit mode handlingJohn Keeping
The RK3288 TRM states that, for 8-bit DDR modes: The CLKDIV register should always be programmed with a value higher than zero (0); that is, a clock divider should always be used for 8-bit DDR mode. In Linux, the driver applies this logic for all SoCs using the driver and does not distinguish RK3288, so presumably this requirement is the same for all other Rockchip SoCs using this IP. Add the necessary code to double the clock frequency when 8-bit DDR is selected. The dw_mmc core already handles setting CLKDIV correctly given the input clock and desired bus clock. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-02-28tpm: sandbox: Change the return code when device is already openIlias Apalodimas
All the TPM drivers as well as out TCG TIS API for a TPM2.0 device return -EBUSY if the device has already been opened. Adjust the sandbox TPM do return the same error code. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-02-27Merge tag 'v2023.04-rc3' into nextTom Rini
Prepare v2023.04-rc3
2023-02-27mtd: nand: Show reserved block in chip.eraseMichael Trimarchi
The "nand chip.erase" command always printed as bad blocks even in the case of reserved blocks. Reserved blocks are used for storing bad block tables. The patch displays "bbt reserved" when printing reserved blocks in "nand chip.erase" command. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: spinand: Fix display of unknown raw IDPatrice Chotard
In case ID is not found in manufacturer table, the raw ID is printed using %*phN format which is not supported by lib/vsprintf.c. The information displayed doesn't reflect the raw ID return by the unknown spi-nand. Use %02x format instead, as done in spi-nor-core.c. For example, before this patch: ERROR: spi-nand: spi_nand flash@0: unknown raw ID f74ec040 after ERROR: spi-nand: spi_nand flash@0: unknown raw ID 00 c2 26 03 Fixes: 0a6d6bae0386 ("mtd: nand: Add core infrastructure to support SPI NANDs") Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Acked-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: rawnand: brcmnand: fix OOB R/W with Hamming ECCÁlvaro Fernández Rojas
Hamming ECC doesn't cover the OOB data, so reading or writing OOB shall always be done without ECC enabled. This is a problem when adding JFFS2 cleanmarkers to erased blocks. If JFFS2 clenmarkers are added to the OOB with ECC enabled, OOB bytes will be changed from ff ff ff to 00 00 00, reporting incorrect ECC errors. Fixes: 27c5b17cd1b1 ("mtd: nand: add NAND driver "library" for Broadcom STB NAND controller") Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210224080210.23686-1-noltari@gmail.com [Ported to U-Boot from the Linux kernel] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: rawnand: brcmnand: support v2.1-v2.2 controllersÁlvaro Fernández Rojas
v2.1: tested on Netgear DGND3700v1 (BCM6368) v2.2: tested on Netgear DGND3700v2 (BCM6362) Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200522121524.4161539-6-noltari@gmail.com [Ported to U-Boot from the Linux kernel] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: rawnand: brcmnand: rename page sizesÁlvaro Fernández Rojas
Current pages sizes apply to controllers after v3.4 Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200522121524.4161539-4-noltari@gmail.com [Ported to U-Boot from the Linux kernel] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: rawnand: brcmnand: fix CS0 layoutÁlvaro Fernández Rojas
Only v3.3-v5.0 have a different CS0 layout. Controllers before v3.3 use the same layout for every CS. Fixes: 27c5b17cd1b1 ("mtd: nand: add NAND driver "library" for Broadcom STB NAND controller") Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200522121524.4161539-3-noltari@gmail.com [Ported to U-Boot from the Linux kernel] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: rawnand: brcmnand: rename v4 registersÁlvaro Fernández Rojas
These registers are also used on v3.3. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200522121524.4161539-2-noltari@gmail.com [Ported to U-Boot from the Linux kernel] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: rawnand: brcmnand: correctly verify erased pagesÁlvaro Fernández Rojas
The current code checks that the whole OOB area is erased. This is a problem when JFFS2 cleanmarkers are added to the OOB, since it will fail due to the usable OOB bytes not being 0xff. Correct this by only checking that data and ECC bytes aren't 0xff. Fixes: 02b88eea9f9c ("mtd: brcmnand: Add check for erased page bitflips") Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200512082451.771212-1-noltari@gmail.com [Ported to U-Boot from the Linux kernel] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: nand: brcmnand: Add support for flash-dma v0Kamal Dasu
This change adds support for flash dma v0.0. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> [Ported to U-Boot from the Linux kernel] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: rawnand: brcmnand: Fix ecc chunk calculation for erased page bitfipsClaire Lin
In brcmstb_nand_verify_erased_page(), the ECC chunk pointer calculation while correcting erased page bitflips is wrong, fix it. Fixes: 02b88eea9f9c ("mtd: brcmnand: Add check for erased page bitflips") Signed-off-by: Claire Lin <claire.lin@broadcom.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> [Ported to U-Boot from the Linux kernel] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: rawnand: brcmnand: Add support for v7.3 controllerKamal Dasu
This change adds support for brcm NAND v7.3 controller. This controller uses a newer version of flash_dma engine and change mostly implements these differences. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> [Ported to U-Boot from the Linux kernel] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: rawnand: brcmnand: Refactored code to introduce helper functionsKamal Dasu
Refactored NAND ECC and CMD address configuration code to use helper functions. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> [Ported to U-Boot from the Linux kernel] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: nand: Mark reserved blocksAshok Reddy Soma
Reserved blocks are used for storing bad block tables. With "nand bad" command, these reserved blocks are shown as bad blocks. This is leading to confusion when compared with Linux bad blocks. Hence, display "bbt reserved" when printing reserved blocks with "nand bad" command. To acheive this, return 2 which represents reserved from nand_isbad_bbt() instead of 1 in case of reserved blocks and catch it in cmd/nand.c. "nand bad" command display's hexadecimal numbers, so add "0x" prefix. Example log will show up as below. ZynqMP> nand bad Device 0 bad blocks: 0x00400000 0x16800000 0x16c00000 0x17000000 0x3d800000 0x3e400000 0xe8400000 0xff000000 (bbt reserved) 0xff400000 (bbt reserved) 0xff800000 (bbt reserved) 0xffc00000 (bbt reserved) 0x116800000 0x116c00000 0x1ff000000 (bbt reserved) 0x1ff400000 (bbt reserved) 0x1ff800000 (bbt reserved) 0x1ffc00000 (bbt reserved) Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Acked-By: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-23ARM: tegra: provide default USB gadget setupMaxim Schwalm
All Nvidia boards use the same manufacturer, vendor ID and product ID for the gadgets. Make them the defaults to remove some boilerplate from the defconfigs. Inspired by commit e02687bda96c ("sunxi: provide default USB gadget setup") which did the same for Allwinner boards. Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124 Signed-off-by: Maxim Schwalm <maxim.schwalm@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
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