Age | Commit message (Collapse) | Author |
|
- kernel can now be up to 8MB
- cleanup, e.g. remove any NAND config
- unify with T20 file layout
|
|
Conflicts:
arch/arm/cpu/armv7/tegra3/warmboot_avp.c
arch/arm/include/asm/arch-tegra/clk_rst.h
|
|
tegra: add enterrcm command
Tegra's boot ROM supports a mode whereby code may be downloaded and flash
programmed over a USB connection. On dev boards, this is typically entered
by holding down a "force recovery" button and resetting the CPU. However,
not all boards have such a button (one example is the Compulab Trimslice),
so a method to enter RCM from software is useful.
This change implements the command "enterrcm" to do this, and enables it
for all Tegra boards by default. Even on boards other than Trimslice,
controlling this over a UART may be useful, e.g. to allow simple remote
control without the need for mechanical button actuators, or hooking up
relays/... to the button.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
|
As the kernel recently passed the 4 MB size limit simply copying 4 MB
won't quite cut it. Increase to 8 MB for now. In the future properly
parsing the SD card's partition table would be the way to go.
|
|
Rather than relying on hard-coded offsets actually make use of
partition table parsing implementation.
|
|
Change SD boot bootdevice in environment variable sdargs from mmcblk3p1
to mmcblk0p1 due to later kernels using a different numbering scheme.
While at it clean-up some white space indentation stuff.
|
|
User space tools like init just use last console kernel boot argument
as their one and only console. Re-order them in order to output boot
messages on serial debug console.
|
|
|
|
0x108000/0x80108000 is used as tegra2/tegra3's default boot loader entry
address. This change makes u-boot to comply with nvidia standard flash tools.
BUG=none
TEST=run cros_write_firmware with local build u-boot. Kernel boots up
fine.
Change-Id: I55e9b5d1847cf7e6a94d362935deef5f6855ba5a
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/21979
Reviewed-by: Simon Glass <sjg@chromium.org>
|
|
The cros_write_firmware has updated flash script command 'crc32' with -v
option. To support this change, u-boot needs to be built with
CONFIG_CRC32_VERIFY for seaboard.
BUG=none
TEST=run cros_write_firmware with local build u-boot.
Change-Id: I49046ce2424c4624a335af32051421e44bd388bb
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/21420
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Mark Zhang <markz@nvidia.com>
Reviewed-by: Wei Ni <wni@nvidia.com>
|
|
This change allows to build a customized u-boot image, which includes
networking capabilities, provides diagnostic commands and supports
command line editing. These features are necessary to facilitate the
factory flow.
This image needs to be clearly distinguishable by ChromeOS. This is
achieved by modifying the value presented by the BINF.3 ACPI object.
To build this modified image one needs to add BUILD_FACTORY_IMAGE=1 to
the make invocation line.
BUG=chrome-os-partner:7952
TEST=manual
. build the new firmware image as follows:
USE='pcserial factory-mode' emerge-link chromeos-u-boot \
chromeos-coreboot chromeos-bootimage
. program the new image on the Link target with ChromeOS installed
on the SSD and restart it
. observe the target stop at u-boot command prompt (boot >)
. connect the target to an Ethernet network with a DHCP server
using a USB Ethernet dongle
. run the following commands at the u-boot prompt
boot > usb start
(Re)start USB...
USB: Register 203007 NbrPorts 7
USB EHCI 1.00
Register 20400b NbrPorts 11
USB EHCI 1.00
8 USB Device(s) found
scanning bus for storage devices... 0 Storage Device(s) found
scanning bus for ethernet devices... 1 Ethernet Device(s) found
boot > dhcp
Waiting for Ethernet connection... done.
BOOTP broadcast 1
BOOTP broadcast 2
[a few warnings of unsupported DHCP options]
DHCP client bound to address 172.22.75.25
Using asx0 device
TFTP from server 172.16.255.7; our IP address is 172.22.75.25; sending through gateway 172.22.75.254
Filename 'pxelinux.0'.
Load address: 0x100000
Loading: ##
done
Bytes transferred = 15840 (3de0 hex)
boot >
. start ChromeOS on the target by issuing
vboot_twostop
. once ChromeOS boots check the mainfw_type crossystem reported value
localhost ~ # echo $(crossystem mainfw_type)
netboot
localhost ~ #
Change-Id: I1c50517754b6b5f773e432b9adec4b290f303e6f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/21071
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
BUG=chrome-os-partner:8180
TEST=Built and booted on emeraldlake2 and Stumpy.
Change-Id: If14ff4930015fae36d421fd30ab5bd126c464db9
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/18059
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
|
|
enable CONFIG_TEGRA_LP0 and CONFIG_TEGRA3_WARMBOOT
BUG=chromium-os:23496
TEST=build and boot on Cardhu
Change-Id: If21303468193c7f5f6ba1c0c0b7cd0ccb5a08c0e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/13801
|
|
enable CONFIG_TEGRA_LP0 and CONFIG_TEGRA3_WARMBOOT
BUG=chromium-os:23496
TEST=build and boot on Waluigi
Change-Id: I622d228d02767954ffa7e101ad6f5f5fb1146702
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/13802
|
|
BUG=chromium-os:23496
TEST=build and boot on Waluigi, Cardhu by enabling
CONFIG_TEGRA_LP0 and CONFIG_TEGRA3_WARMBOOT.
odification of the work done by:
a. Jimmy Zhang <jimmzhang@nvidia.com>
b. Yen Lin <yelin@nvidia.com>
c. Wei Ni <wni@nvidia.com>
Change-Id: If2fa63ccd23341694955bca25fb5cfc4a8a805ad
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/13800
|
|
BUG=chromium-os:23496
TEST=build for Cardhu, Waluigi and Seaboard
Change-Id: I32dbfa02ac1d6954b3a7e515914fbc0b6695f98b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14683
|
|
split the LP0 code for tegra2 into common
LP0 code and chip specific warm boot code
BUG=chromium-os:23496
TEST=build for Seaboard
Change-Id: Ie04bf9ac17482a37afd0f4515dc3aafeb4f48ae7
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/15883
|
|
This reverts commit 4c7502242627f64d91432cb4958be5f93f65fbff
Don't think this is the cause of http://code.google.com/p/chromium-os/issues/detail?id=26116, but it was in the same batch so I'm reverting in the process.
Change-Id: Icc013ced6c22e29d569ee4ca8ef73522154ec1a8
Reviewed-on: https://gerrit.chromium.org/gerrit/15561
Reviewed-by: Brian Harring <ferringb@chromium.org>
Tested-by: Brian Harring <ferringb@chromium.org>
|
|
split the LP0 code for tegra2 into common
LP0 code and chip specific warm boot code
BUG=chromium-os:23496
TEST=build for Seaboard
Change-Id: Id9756c08f61502affa8beee636d883d01468e6ec
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/13799
|
|
Enables common LCD support for Tegra2 and Tegra3
BUG=chromium-os:23496
TEST=Built ok for Cardhu, Waluigi and Seaboard.
Change-Id: I938824045440cc4964c2ac6bf727a90ee5f129b4
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14692
|
|
Helps kernel developers using kernels with custom
ramdisk images. Some developers who would like to
work with upstream kernel specifically requested
for this feature, since it helps them during early
development days.
BUG=chromium-os:23496
TEST=build and boot on Cardhu, Waluigi
Change-Id: I698da421bf924a5c86229a80c0a25021d3e6f046
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14475
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Ready: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
|
|
Add Keyboard config options CONFIG_TEGRA_KEYBOARD and CONFIG_KEYBOARD.
BUG=chromium-os:23496
TEST=Tested on Waluigi. key press echoes the key on console.
Build OK for cardhu.
Change-Id: I7856f2d22c935a4a94f91c67263913e1240f25b5
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/13790
Commit-Ready: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
|
|
Replace Tegra2 specific tag "CONFIG_TEGRA2_KEYBOARD" by
common tag "CONFIG_TEGRA_KEYBOARD" to include tegra keyboard
driver.
BUG=chromium-os:23496
TEST=Build ok for Cardhu,Seaboard and Waluigi.
Change-Id: Idd16990ba525b8391c3c14e37efd5587f09a25c8
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/13860
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
|
|
BUG=chromium-os:23496
TEST=Built ok for Cardhu, Waluigi and Seaboard. Tested on Waluigi.
Change-Id: Ifb4deba51137251ea0564bf3e66f33f7c62420e4
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14701
Reviewed-by: Simon Glass <sjg@chromium.org>
|
|
BUG=chromium-os:23496
TEST=Build ok for Waluigi,Cardhu and Seaboard.
"printenv bootargs" shows the changed kernel arg on Waluigi.
Change-Id: I87934f9a887c367098152ac753f98681760ec160
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/13797
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Commit-Ready: Che-Liang Chiou <clchiou@chromium.org>
Tested-by: Olof Johansson <olofj@chromium.org>
|
|
The code which provides GPT support has some potential security issues in it.
Since we're not using it anyway, we might as well just turn it off.
BUG=chromium-os:25041
BUG=chromium-os:25042
TEST=Built and booted on Lumpy with various options turned on and off.
Signed-off-by: Gabe Black <gabeblack@google.com>
Change-Id: I7618ba1a34e553094c1cd96bfe892c9c6d0f02ba
Reviewed-on: https://gerrit.chromium.org/gerrit/14180
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
|
|
Allow to reconfigure properly the USB keyboard driver when we enumerate
several times the USB devices and its position in the device tree has
changes.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:7188 chrome-os-partner:7430 chrome-os-partner:7432
chrome-os-partner:7559
TEST=On lumpy with usb keyboard configured, run in recovery mode, insert
a bad key, press tab, remove the key, press tab. The recovery info are
displayed properly.
Change-Id: Ief5e25879fe75fb6371a089a310c5d6af662252f
Reviewed-on: https://gerrit.chromium.org/gerrit/14188
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
|
|
The mmc0_tftpboot option reads a kernel using TFTP but then boots from
eMMC. This allows kernel development without resorting to NFS root (which
changes some parts of the boot process).
BUG=chromium-os:22938
TEST=build and boot on Kaen
Change-Id: I23c0890f76dc63dde128d7137d8891341761c884
Reviewed-on: https://gerrit.chromium.org/gerrit/13280
Commit-Ready: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
|
|
The vboot command makes sure that the LCD init is completed so we don't
need this in board_late_init().
Overall the LCD init optimization reduces boot time by about 150ms.
BUG=chromium-os:22938
TEST=build and boot on Kaen
Change-Id: Idcefb81108d0499bb208f8b3d90df65ca4cb6349
Reviewed-on: https://gerrit.chromium.org/gerrit/13206
Commit-Ready: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
|
|
LCD final init is now kept in board_late_init(), so we need to enable
this feature in the config.
BUG=chromium-os:22938
TEST=build and boot on Kaen
Change-Id: Ib895c2768359439349714805cea6ff636c2307b3
Reviewed-on: https://gerrit.chromium.org/gerrit/13214
Commit-Ready: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
|
|
The GetReport request isn't implemented in all keyboards, so
use interrupt transfers instead.
BUG=chrome-os-partner:5752
TEST=Use USB keyboard in u-boot (recovery mode)
Change-Id: Ided3289ef86ee9899813582c9f137526399ad2f8
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: https://gerrit.chromium.org/gerrit/13491
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
|
|
Turning on this option saves about 20ms boot time.
BUG=chromium-os:22938
TEST=build and boot on Kaen
Change-Id: I06ec0ae0da4afc208ca7952dfa42e725f5a67d4c
Reviewed-on: https://gerrit.chromium.org/gerrit/13208
Commit-Ready: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
|
|
BUG=chromium-os:23496
TEST=built and booted Cardhu to cmd prompt; USB, MMC, SPI all work.
This build is to allow developers that don't have a Waluigi to
still contribute to porting/upstreaming T30 U-Boot code/patches.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Change-Id: I5978cbe33bfc9329f420c32eb5ca97b9b302029c
Reviewed-on: https://gerrit.chromium.org/gerrit/12932
Reviewed-by: Simon Glass <sjg@chromium.org>
|
|
BUG=chromium-os:23496
TEST=build and boot Waluigi T30. Usb detects devices OK.
usb tree, usb part, ext2ls usb and ext2load usb work as expected.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Change-Id: I40910e0c770bb33171ad9c8b4e5a6baaaac4a7df
Reviewed-on: https://gerrit.chromium.org/gerrit/12392
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Commit-Ready: Simon Glass <sjg@chromium.org>
|
|
In making config names consistent, this commit renames configs following
the "chromeos_${BOARD}" naming convention.
The old config names are kept before portage overlays are set to the new
config names to prevent builders from break. They will be removed in
next commit.
BUG=chromium-os:23869
TEST=Run script snippet below successfully
>>>>
for BOARD in lumpy \
stumpy \
tegra2_aebl \
tegra2_arthur \
tegra2_asymptote \
tegra2_dev-board \
tegra2_dev-board-opengl \
tegra2_kaen \
tegra2_seaboard \
tegra2_wario \
waluigi \
x86-alex \
x86-alex_he \
x86-mario \
x86-mario64
do
ebuild-${BOARD} /path/to/chromeos-u-boot-9999.ebuild configure
done
<<<<
Change-Id: I984bea648f6d8384facce9771a7a5de3b169108c
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/12671
Reviewed-by: Simon Glass <sjg@chromium.org>
|
|
This setting is now in the fdt, so remove the CONFIG item.
BUG=chromium-os:23496
TEST=build and boot on Seaboard, T33, Kaen
Change-Id: I336a6cc2140c725fdda85330efe617f82f205a90
Reviewed-on: https://gerrit.chromium.org/gerrit/12250
Commit-Ready: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
|
|
New device ID range is included to allow the SPI driver to use the
Panther Point based controller and a new device ID is checked when
attaching the AHCI controller.
BUG=chrome-os-partner:7112
TEST=manual
After this change the top of the tree ChromeOS can be booted on IVB
reworked Stumpy platforms.
Change-Id: Ia41c17b58337cde2d041990b3d1c9da37c0cd92c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/12606
|
|
Enable the compilation of USB keyboard driver code and the associated
polling code to detect keypress with the EHCI controller.
BUG=chrome-os-partner:5752
TEST=tested on Stumpy and Lumpy, with and without usb-keyboard set
in the device tree, check Ctrl+U, Ctrl+D and space are working as expected.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Change-Id: I424758ad6a30d01b5858ddaff6e4494a40e79f83
Reviewed-on: https://gerrit.chromium.org/gerrit/12582
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
|
|
We don't need the default serial clock now, since we try with both
options.
BUG=chromium-os:23496
TEST=build and boot on Seaboard, T33, Kaen
Change-Id: I68a80174e10b299c46742d36291d839ea9fa6d7c
Reviewed-on: https://gerrit.chromium.org/gerrit/12249
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Commit-Ready: Simon Glass <sjg@chromium.org>
|
|
This reverts commit fab63e9aacc49a3d224df47b6d0e23dc6b73de40.
Change-Id: I4ce3622871374baa7da19263cbe38603b4f9e356
Reviewed-on: https://gerrit.chromium.org/gerrit/11943
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Commit-Ready: Simon Glass <sjg@chromium.org>
|
|
Perhaps due to a toolchain change or the recent TFTP changes, U-Boot
no longer fits in the space available. This removes NAND support
to give us time to expand the space and/or fix the toolchain.
TBR=U-Boot suddenly grew for no immediately obvious reason, quick fix.
http://build.chromium.org/p/chromiumos/builders/tegra2%20seaboard%20full/builds/924/steps/cbuildbot/logs/stdio
TEST=build U-Boot and see that it is about 40KB smaller.
Change-Id: Iec02cc4da57cac7e79355714000f3e5d31c326c4
Reviewed-on: https://gerrit.chromium.org/gerrit/11895
Reviewed-by: Yasuhiro Matsuda <mazda@chromium.org>
Commit-Ready: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
|
|
BUG=chromium-os:21033
TEST=run `sf erase, write` and `sf read` on Waluigi
verify the data it reads from SPI flash matches that it writes to
Change-Id: Ibeefd3183e4fa367d68d0035a818e1c166e6d59d
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/11473
Commit-Ready: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Tested-by: Che-Liang Chiou <clchiou@chromium.org>
|
|
BUG=chromium-os:21033
TEST=run `sf erase, write` and then `sf read` on seaboard
verify the data it reads from SPI flash matches that it writes to
Change-Id: I1b04afa4b54738cd93be29b70f428bdc3e6b234f
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/11472
Commit-Ready: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Tested-by: Che-Liang Chiou <clchiou@chromium.org>
|
|
BUG=chromium-os:21033
TEST=build seaboard successfully
Change-Id: Idbfbdbf0bdb1070f4a2b5f8205c1caff6ef0c811
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/11471
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
|
|
On X86 systems the hardware maps the bootprom SPI flash chip into the
top of memory address range. This could be used for accessing all
information in the SPI flash.
The vboot-reference code requires access to FMAP sections containing
cryptographic information, and as of today, u-boot reads the whole
sections, which are 64 KB in size, even though the actual areas
accessed by vboot-reference are much smaller.
A much faster way of accessing this information would be just passing
around pointers to the appropriate memory areas. This would eliminate
one copy, and also would make sure that only the areas actually
accessed get fetched from SPI flash.
This patch provides this ability trying to keep code changes to a
minimum.
New feature is enabled by defining CONFIG_HARDWARE_MAPPED_SPI. The
firmware storage API for file reads changes when the new configuration
option is set: a pointer to pointer to buffer is passed to the
read_spi() function instead of a pointer to buffer. When the new
feature is enabled the read_spi() function sets the pointer value to
point to the requested data instead of copying the data into the
buffer.
A new data type is introduced (read_buf_type), which is set to be a
(void *) if the new feature is not enabled, or (void **) otherwise.
This type is used as the buffer pointer in the spi_read() function.
Code allocating/freeing buffers used to keep data read from SPI flash
is now conditionally compiled.
Call sites for the spi_read() function are modified to adjust the
buffer pointer parameter (pass the address of the parameter instead of
the parameter, when the new feature is enabled).
gbb field access functions can be aliased to gbb_init(), as they all
in fact do the same - read a certain section of the gbb area.
This change does not benefit the ARM implementations, and makes the
code more complicated that it should be. Some u-boot rearchitecture
along with vboot_reference API enhancements could address this. A
tracking issue
(http://code.google.com/p/chromium-os/issues/detail?id=22528) has been
opened for that.
BUG=chrome-os-partner:6585, chromium-os:22528
TEST=manual
. build a new stumpy firmware image
. boot the stumpy, observe it start up chromeos.
. assess the boot timing using the cbmem.py utility (this
modification shaves in excess of 100ms off the boot time).
. disable the new feature, build a stumpy image, observe that is
still boots chromeOs.
. run emerge-terga2_kaen chromeos-u-boot to confirem that ARM
version builds cleanly.
Change-Id: I4e6ab530d24f5771b5a86a48d3f3135101b469a6
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/11152
|
|
With this set of config options we can now boot the kernel. With
the kernel I have, it doesn't work yet, but at least it prints out
some messages to the UART.
BUG=chromium-os:21540
TEST=If I have a reasonable kernel in MMC1, I see that it can boot
quite a ways into the kernel w/ autoboot.
Change-Id: I5918fff3d48f2ff9f2bac9261c84e08e60a1560a
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/10675
|
|
BUG=chromium-os:21540
TEST=Able to use mmc.
Change-Id: I1d566f08f9dd115b5be1a05ffa0ff07b508e0cee
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/10663
|
|
The MMC reader looks like a USB device, so we don't need to support generic
MMC devices directly.
BUG=chrome-os-partner:6585
TEST=Built and booted on Stumpy.
Change-Id: Id5729cd9d51e0c4cb2570b9b452f96bd23764b85
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/10755
Commit-Ready: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
|
|
We aren't currently planning to have network support in production firmware. If
we need it at some point, we can easily turn that support back on.
BUG=chrome-os-partner:6585
TEST=Built and booted on Stumpy
Change-Id: Iad265bb2bbae5360135eaa8577cc6dfde95045f9
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/10754
Commit-Ready: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
|
|
Disable it by default since we're using the SCSI interface now. Being able to
turn IDE back on later might be necessary if we haven't gotten AHCI support
working on a new platform yet.
BUG=chrome-os-partner:6585
TEST=Built and booted on Stumpy.
Change-Id: I07e80dc2673529f3f2ec52431e1c0958511539b0
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/10753
Commit-Ready: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
|