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2014-04-16colibri_t20: fix/hack sd boot environmentMarcel Ziswiler
We wrongly set an obsolete define so the U-Boot environment ended up at the wrong location on the SD card. Add a hack introducing a short delays before doing MMC_CMD_SET_BLOCKLEN as otherwise all 4GB Kingston or SanDisk cards I have failed. While at it fix the USB port naming in the device tree comments to adhere to the standard Colibri convention.
2014-03-14colibri_t20: enable initrd atag supportMarcel Ziswiler
Enable CONFIG_INITRD_TAG which allows passing initrd ATAGs to the Linux kernel required for initial RAM disk support.
2014-03-12apalis/colibri_t20/30: hw boot partition supportMarcel Ziswiler
The new production lot of Apalis T30 2GB V1.0C now features the new SK Hynix H26M42003GMR rather than Hynix H26M42002GMR. Even though both chips feature the same silicon they differ in respective eMMC firmware and therefore have a different hardware boot partition layout. This patch enables hardware boot partition support (via 'mmc dev [dev] [part]' command) and handles NVIDIA's proprietary NvFlash/Fastboot\ behaviour now putting their partition table in the second boot partition rather than the regular user area. While at it also get rid of the spurious 'video=tegrafb' kernel boot argument, adjust the optional ubiargs and add 'noatime' to the usbargs.
2014-01-30apalis/colibri_t20/t30: fix environmentMarcel Ziswiler
Add some missing back slashes causing compilation failures.
2014-01-30apalis/colibri_t20/t30: add vidargs and fix usbboot optionMarcel Ziswiler
Add default VESA VGA vidargs for our now modedb enabled kernel. This allows easy specifying an alternate parallel RGB resolution. Fix usbboot option to be more in-line with how we do optional MMC/SD card boot on Colibri VF50/VF61. Loads the uimage kernel from the first partition being formatted as VFAT and instructs the kernel to mount the second partition formatted as ext3 as root file system. While at it further checkpatchify our common board file.
2013-08-12apalis/colibri_t20/30: rename shell promptT30_LinuxImageV2.0Beta3_20130820Apalis_T30_LinuxImageV2.0Beta2_20130816Marcel Ziswiler
In order to be able to distinguish what hardware one is running on change the U-Boot shell prompt to something more meaningful.
2013-08-12apalis/colibri_t30: implement memory size auto detectionMarcel Ziswiler
In preparation for the new Apalis T30 SKUs implement memory size auto detection based on reading the aperture register set by boot ROM from BCT and a simple mirroring detection. Tested on initial samples of Apalis T30 1GB V1.0A, Apalis T30 2GB V1.0B, Apalis T30 2GB V1.0C and Colibri T30 V1.1C.
2013-05-09apalis/colibri_t20/30: decrease boot delayMarcel Ziswiler
As we have lots of impatient managers lets decrease the default boot delay. One can still enter the interactive U-Boot console by hitting a key just in time of boot/reset. Please note currently at Toradex we from the Linux team concentrate on feature stability rather than fast booting.
2013-05-09apalis_t30: activate DVI-D framebuffer consoleMarcel Ziswiler
As Apalis T30 uses DVI-D aka HDMI as its default external display interface make sure to activate the framebuffer console on there.
2013-05-09apalis_t30: adjust available amount of memoryMarcel Ziswiler
Forgot to actually adjust the amount of available memory in the previous commit. Wouldn't it be nice to actually be able to use the full 2GB?
2013-05-09apalis_t30: initial integrationMarcel Ziswiler
Add initial Apalis T30 support based off our current Colibri T30 implementation: - Updated machine ID. - USB host USBH2 and USBH3 support. Note: USBO1 support is currently broken. - Updated MMC and SD card support. - Adjusted available amount of memory.
2013-05-01colibri_t30: emmc: change offset handlingMarcel Ziswiler
Rather than relying on hard-coded offsets actually make use of partition table parsing implementation. While at it bring the whole config more in-line with the Colibri T20.
2013-05-01colibri_t20: sdboot: change offset handlingMarcel Ziswiler
Rather than relying on hard-coded offsets actually make use of partition table parsing implementation.
2013-01-08T30: cmdline with rootfs mounted noatime, not the default relatimeMax Krummenacher
2012-12-27T30: cmdline with ext3 rootfs, not ext2T30_LinuxImageV2.0Alpha0_20121227Max Krummenacher
2012-10-31T30: colibri_t30.hMax Krummenacher
- kernel can now be up to 8MB - cleanup, e.g. remove any NAND config - unify with T20 file layout
2012-10-30Merge branch 'chromeos-v2011.06' into colibriMarcel Ziswiler
Conflicts: arch/arm/cpu/armv7/tegra3/warmboot_avp.c arch/arm/include/asm/arch-tegra/clk_rst.h
2012-10-29tegra: add enterrcm commandStephen Warren
tegra: add enterrcm command Tegra's boot ROM supports a mode whereby code may be downloaded and flash programmed over a USB connection. On dev boards, this is typically entered by holding down a "force recovery" button and resetting the CPU. However, not all boards have such a button (one example is the Compulab Trimslice), so a method to enter RCM from software is useful. This change implements the command "enterrcm" to do this, and enables it for all Tegra boards by default. Even on boards other than Trimslice, controlling this over a UART may be useful, e.g. to allow simple remote control without the need for mechanical button actuators, or hooking up relays/... to the button. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-25colibri_t20: fix SD bootMarcel Ziswiler
As the kernel recently passed the 4 MB size limit simply copying 4 MB won't quite cut it. Increase to 8 MB for now. In the future properly parsing the SD card's partition table would be the way to go.
2012-10-18colibri_t20: nand: change offset handlingMarcel Ziswiler
Rather than relying on hard-coded offsets actually make use of partition table parsing implementation.
2012-10-18colibri_t20: fix SD boot bootdeviceMarcel Ziswiler
Change SD boot bootdevice in environment variable sdargs from mmcblk3p1 to mmcblk0p1 due to later kernels using a different numbering scheme. While at it clean-up some white space indentation stuff.
2012-10-16colibri_t20: modify order of console boot argumentMarcel Ziswiler
User space tools like init just use last console kernel boot argument as their one and only console. Re-order them in order to output boot messages on serial debug console.
2012-08-22Initial Toradex Colibri T20 L4T R15 support.T20_LinuxImageV2.0Alpha1_20120808Marcel Ziswiler
2012-07-18tegra: config: Change load entry to 0x108000/0x80108000Jimmy Zhang
0x108000/0x80108000 is used as tegra2/tegra3's default boot loader entry address. This change makes u-boot to comply with nvidia standard flash tools. BUG=none TEST=run cros_write_firmware with local build u-boot. Kernel boots up fine. Change-Id: I55e9b5d1847cf7e6a94d362935deef5f6855ba5a Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/21979 Reviewed-by: Simon Glass <sjg@chromium.org>
2012-04-30arm: tegra2: seaboard: Enable CRC32 v optionJimmy Zhang
The cros_write_firmware has updated flash script command 'crc32' with -v option. To support this change, u-boot needs to be built with CONFIG_CRC32_VERIFY for seaboard. BUG=none TEST=run cros_write_firmware with local build u-boot. Change-Id: I49046ce2424c4624a335af32051421e44bd388bb Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/21420 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Mark Zhang <markz@nvidia.com> Reviewed-by: Wei Ni <wni@nvidia.com>
2012-04-25Provide alternative config for netbootingVadim Bendebury
This change allows to build a customized u-boot image, which includes networking capabilities, provides diagnostic commands and supports command line editing. These features are necessary to facilitate the factory flow. This image needs to be clearly distinguishable by ChromeOS. This is achieved by modifying the value presented by the BINF.3 ACPI object. To build this modified image one needs to add BUILD_FACTORY_IMAGE=1 to the make invocation line. BUG=chrome-os-partner:7952 TEST=manual . build the new firmware image as follows: USE='pcserial factory-mode' emerge-link chromeos-u-boot \ chromeos-coreboot chromeos-bootimage . program the new image on the Link target with ChromeOS installed on the SSD and restart it . observe the target stop at u-boot command prompt (boot >) . connect the target to an Ethernet network with a DHCP server using a USB Ethernet dongle . run the following commands at the u-boot prompt boot > usb start (Re)start USB... USB: Register 203007 NbrPorts 7 USB EHCI 1.00 Register 20400b NbrPorts 11 USB EHCI 1.00 8 USB Device(s) found scanning bus for storage devices... 0 Storage Device(s) found scanning bus for ethernet devices... 1 Ethernet Device(s) found boot > dhcp Waiting for Ethernet connection... done. BOOTP broadcast 1 BOOTP broadcast 2 [a few warnings of unsupported DHCP options] DHCP client bound to address 172.22.75.25 Using asx0 device TFTP from server 172.16.255.7; our IP address is 172.22.75.25; sending through gateway 172.22.75.254 Filename 'pxelinux.0'. Load address: 0x100000 Loading: ## done Bytes transferred = 15840 (3de0 hex) boot > . start ChromeOS on the target by issuing vboot_twostop . once ChromeOS boots check the mainfw_type crossystem reported value localhost ~ # echo $(crossystem mainfw_type) netboot localhost ~ # Change-Id: I1c50517754b6b5f773e432b9adec4b290f303e6f Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/21071 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2012-03-29Make u-boot recognize full range of PPT LPC controllersVadim Bendebury
The full range of LPC controllers should be accepted by u-boot when looking for the SPI controller. The values come from Intel's Panther_Point_EDS_v072.pdf (document #472178). BUG=chrome-os-partner:7734 TEST=manual . program the new image on the target . reboot it and observe coming up to ChromeOS login screen Change-Id: Id8f7068c3b48885f868a1f30e7927e678d2154b6 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/19147 Reviewed-by: Jon Salz <jsalz@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/19310 Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
2012-03-13gen: Make the SCSI command aware of READ CAPACITY (16) and how to use itGabe Black
The generic SCSI code in U-Boot was only aware of the READ CAPACITY (10) SCSI command which can detect the size of disks up to 2TB in size. If that size is exceeded, it should then try the READ CAPACITY (16) command which returns a 64 bit block count value. BUG=chrome-os-partner:8180 TEST=In conjunction with the next change, built and booted into ChromeOS on the Emerald Lake 2 CRB with a 250 GB SSD. Did the same but forced the READ CAPACITY (10) command to saturate and the code to fall back to READ CAPACITY (16). Note that this code has not be tested with a real SCSI disk, just the AHCI code pretending to be a SCSI disk as it historically has. Change-Id: Ia0ee3fa1264649f25065658d5d368101d39ce614 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/18060 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
2012-03-13x86: config: Turn on the CONFIG_SYS_64BIT_LBA option for corebootGabe Black
BUG=chrome-os-partner:8180 TEST=Built and booted on emeraldlake2 and Stumpy. Change-Id: If14ff4930015fae36d421fd30ab5bd126c464db9 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/18059 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
2012-02-27tegra: configs: enable warm boot on CardhuVarun Wadekar
enable CONFIG_TEGRA_LP0 and CONFIG_TEGRA3_WARMBOOT BUG=chromium-os:23496 TEST=build and boot on Cardhu Change-Id: If21303468193c7f5f6ba1c0c0b7cd0ccb5a08c0e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/13801
2012-02-27tegra: configs: enable warm boot on WaluigiVarun Wadekar
enable CONFIG_TEGRA_LP0 and CONFIG_TEGRA3_WARMBOOT BUG=chromium-os:23496 TEST=build and boot on Waluigi Change-Id: I622d228d02767954ffa7e101ad6f5f5fb1146702 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/13802
2012-02-27arm: tegra3: add warmboot code needed for LP0Varun Wadekar
BUG=chromium-os:23496 TEST=build and boot on Waluigi, Cardhu by enabling CONFIG_TEGRA_LP0 and CONFIG_TEGRA3_WARMBOOT. odification of the work done by: a. Jimmy Zhang <jimmzhang@nvidia.com> b. Yen Lin <yelin@nvidia.com> c. Wei Ni <wni@nvidia.com> Change-Id: If2fa63ccd23341694955bca25fb5cfc4a8a805ad Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/13800
2012-02-16arm: config: tegra: add bct offset addressVarun Wadekar
BUG=chromium-os:23496 TEST=build for Cardhu, Waluigi and Seaboard Change-Id: I32dbfa02ac1d6954b3a7e515914fbc0b6695f98b Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/14683
2012-02-14arm: tegra2: split LP0 code to help future chipsVarun Wadekar
split the LP0 code for tegra2 into common LP0 code and chip specific warm boot code BUG=chromium-os:23496 TEST=build for Seaboard Change-Id: Ie04bf9ac17482a37afd0f4515dc3aafeb4f48ae7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/15883
2012-02-08Revert "arm: tegra2: split LP0 code to help future chips"Brian Harring
This reverts commit 4c7502242627f64d91432cb4958be5f93f65fbff Don't think this is the cause of http://code.google.com/p/chromium-os/issues/detail?id=26116, but it was in the same batch so I'm reverting in the process. Change-Id: Icc013ced6c22e29d569ee4ca8ef73522154ec1a8 Reviewed-on: https://gerrit.chromium.org/gerrit/15561 Reviewed-by: Brian Harring <ferringb@chromium.org> Tested-by: Brian Harring <ferringb@chromium.org>
2012-02-08arm: tegra2: split LP0 code to help future chipsVarun Wadekar
split the LP0 code for tegra2 into common LP0 code and chip specific warm boot code BUG=chromium-os:23496 TEST=build for Seaboard Change-Id: Id9756c08f61502affa8beee636d883d01468e6ec Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/13799
2012-02-07tegra: Rename "CONFIG_VIDEO_TEGRA2" to "CONFIG_VIDEO_TEGRA"Puneet Saxena
Enables common LCD support for Tegra2 and Tegra3 BUG=chromium-os:23496 TEST=Built ok for Cardhu, Waluigi and Seaboard. Change-Id: I938824045440cc4964c2ac6bf727a90ee5f129b4 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/14692
2012-02-07arm: Tegra3: Add initrd ATAG support to all Tegra3Varun Wadekar
Helps kernel developers using kernels with custom ramdisk images. Some developers who would like to work with upstream kernel specifically requested for this feature, since it helps them during early development days. BUG=chromium-os:23496 TEST=build and boot on Cardhu, Waluigi Change-Id: I698da421bf924a5c86229a80c0a25021d3e6f046 Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/14475 Reviewed-by: Simon Glass <sjg@chromium.org> Commit-Ready: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
2012-02-07tegra: config: waluigi: Enable keyboard support for WaluigiPuneet Saxena
Add Keyboard config options CONFIG_TEGRA_KEYBOARD and CONFIG_KEYBOARD. BUG=chromium-os:23496 TEST=Tested on Waluigi. key press echoes the key on console. Build OK for cardhu. Change-Id: I7856f2d22c935a4a94f91c67263913e1240f25b5 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/13790 Commit-Ready: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
2012-02-06tegra: config: Rename CONFIG_TEGRA2_KEYBOARDPuneet Saxena
Replace Tegra2 specific tag "CONFIG_TEGRA2_KEYBOARD" by common tag "CONFIG_TEGRA_KEYBOARD" to include tegra keyboard driver. BUG=chromium-os:23496 TEST=Build ok for Cardhu,Seaboard and Waluigi. Change-Id: Idd16990ba525b8391c3c14e37efd5587f09a25c8 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/13860 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-02-05tegra: waluigi: enable LCD supportPuneet Saxena
BUG=chromium-os:23496 TEST=Built ok for Cardhu, Waluigi and Seaboard. Tested on Waluigi. Change-Id: Ifb4deba51137251ea0564bf3e66f33f7c62420e4 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/14701 Reviewed-by: Simon Glass <sjg@chromium.org>
2012-01-25AHCI: cosmetics and cleanupStefan Reinauer
- print the correct speed - print all the AHCI capability flags (information taken from Linux kernel driver) - clean up some comments Signed-off-by: Stefan Reinauer <reinauer@google.com> BUG=chrome-os-partner:7714 TEST=See the following string in bios_log: AHCI 0001.0300 32 slots 6 ports 6 Gbps 0x3 impl SATA mode Change-Id: Ib32dbeddd0714359948e2bec033b2ec7aabbdb10 Reviewed-on: https://gerrit.chromium.org/gerrit/14754 Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Ready: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2012-01-25vbexport: report correct number of scsi drivesStefan Reinauer
Right now our code makes the assumption that there always is one SCSI drive in the system (the AHCI attached SDD). However, this might not be the case. This patch prevents vboot from using an uninitialized disk entry when instead it should go into recovery mode. BUG=chrome-os-partner:7716 TEST=none Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I761bbb3c92a60d4205a217c7b025f699deed83b0 Reviewed-on: https://gerrit.chromium.org/gerrit/14753 Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Ready: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2012-01-19Enable frequency selection in VbExBeep().Bill Richardson
BUG=none TEST=manual In dev-mode, press "Ctrl-U" with no USB stick inserted. If "crossystem dev_boot_usb" is 0, you'll hear two 400Hz beeps. If "crossystem dev_boot_usb" is 1, you'll hear one 200Hz beep. Signed-off-by: Bill Richardson <wfrichar@google.com> Change-Id: Ifd45a067ec8b922863331f13f3f4525ef40f7346 Reviewed-on: https://gerrit.chromium.org/gerrit/14529 Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Commit-Ready: Bill Richardson <wfrichar@chromium.org>
2012-01-18Introduce arch_phys_memset which works like memset but on physical memoryGabe Black
The default implementation of this function is just memset, but other implementations will be needed when physical memory isn't accessible by U-Boot using normal addressing mechanisms. BUG=chrome-os-partner:7579 TEST=From the original, larger patch: Built and booted on Lumpy, Stumpy, and Kaen. Looked at the log to see that the regions in high memory are listed as cleared. Artificially injected a range to "clear" with 0xA5 and then 0x5A which was over the framebuffer and covered part or all of the screen on Lumpy. Verified that the screen was partially or completely filled with an appropriate looking color. Had U-Boot print the PDTs it was generating to verify that the high address bits were preserved. Identity mapped only some of memory and verified that things that should be mapped were accessible and things that shouldn't be weren't. Signed-off-by: Gabe Black <gabeblack@google.com> Change-Id: Ie1ba5bbb8ee2847f450d0057611deee397c316cf Reviewed-on: https://gerrit.chromium.org/gerrit/14417 Reviewed-by: Gabe Black (Do Not Use) <gabeblack@google.com> Tested-by: Gabe Black (Do Not Use) <gabeblack@google.com>
2012-01-18configs: waluigi: remove pmuboard kernel argPuneet Saxena
BUG=chromium-os:23496 TEST=Build ok for Waluigi,Cardhu and Seaboard. "printenv bootargs" shows the changed kernel arg on Waluigi. Change-Id: I87934f9a887c367098152ac753f98681760ec160 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/13797 Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Commit-Ready: Che-Liang Chiou <clchiou@chromium.org> Tested-by: Olof Johansson <olofj@chromium.org>
2012-01-17Add generation of ANSI 3.64 escape sequences.Terry Lambert
This adds support for generation of ANSI 3.64 escape sequences to the PS/2 keyboard driver. This change significantly refactors the code: o It adds an FSA to support 0xE0 and 0xE1 multibyte PS/2 scan code sequences. o It converts the PS/2 scan codes to USB scan code values to facilitate sharing upper level code in future changes. Reasons to use USB scan codes: o Standard o Simple conversion to ASCII / ANSI 3.64 o Ability to share complex processing / state code o Shared international keymaps in higher level code o It adds an ANSI 3.64 escape sequence generator for USB special keys; the intent of doing this is to allow the transparent use of PS/2, USB, and network or serial devices using the same upper level u-boot clients. o It adds an input FIFO which is an almost verbatim copy of the Tegra matrix keyboard driver; future changes are expected to share the FIFOcode among all keyboard drivers. International keyboard support is expected to be handled at a higher layer in the future, using a much smaller NRCS (National Replacement Character Set) table instead of a duplicat table. Combined, the changes reduce the overall source file size by about 5K, and removes about 4K from the data segment as well. Note: Use of typedef for FSA states allows compiler to prohibit switch statement without default case from omitting states. BUG=chrome-os-partner:6580 TEST=Removed backslash from generated 3.64 sequences, stopped boot at command line, verified character sequence generation. Signed-off-by: tlambert@chromium.org Change-Id: I00200c5ccefd44679335fb643b21794e5d77663a modified: drivers/input/i8042.c modified: include/i8042.h Change-Id: I22c692f7bd65da5848908fc71c6cd7d04753f135 Reviewed-on: https://gerrit.chromium.org/gerrit/14218 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Gabe Black (Do Not Use) <gabeblack@google.com> Tested-by: Terry Lambert <tlambert@chromium.org> Commit-Ready: Terry Lambert <tlambert@chromium.org>
2012-01-13Coreboot: Compile out disk partition and file system codeGabe Black
The code which provides GPT support has some potential security issues in it. Since we're not using it anyway, we might as well just turn it off. BUG=chromium-os:25041 BUG=chromium-os:25042 TEST=Built and booted on Lumpy with various options turned on and off. Signed-off-by: Gabe Black <gabeblack@google.com> Change-Id: I7618ba1a34e553094c1cd96bfe892c9c6d0f02ba Reviewed-on: https://gerrit.chromium.org/gerrit/14180 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org>
2012-01-13Make the memory wipe code handle 64 bit addresses properlyGabe Black
When telling the memory wipe infrastructure about regions it should and shouldn't wipe, some of those addresses may be 64 bits on x86. This change makes the infrastructure pass around those addresses intact instead of truncating them, and then simply ignore the regions that are unaddressable by U-Boot. BUG=None TEST=Built and booted on Lumpy. Built on Kaen Signed-off-by: Gabe Black <gabeblack@google.com> Change-Id: I657cd5480ca9a33614b032bf2a727d1a74d38b48 Reviewed-on: https://gerrit.chromium.org/gerrit/14149 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Commit-Ready: Gabe Black (Do Not Use) <gabeblack@google.com> Tested-by: Gabe Black (Do Not Use) <gabeblack@google.com>
2012-01-13config: coreboot: allow to unregister input devicesVincent Palatin
Allow to reconfigure properly the USB keyboard driver when we enumerate several times the USB devices and its position in the device tree has changes. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:7188 chrome-os-partner:7430 chrome-os-partner:7432 chrome-os-partner:7559 TEST=On lumpy with usb keyboard configured, run in recovery mode, insert a bad key, press tab, remove the key, press tab. The recovery info are displayed properly. Change-Id: Ief5e25879fe75fb6371a089a310c5d6af662252f Reviewed-on: https://gerrit.chromium.org/gerrit/14188 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
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