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2012-08-22Initial Toradex Colibri T20 L4T R15 support.T20_LinuxImageV2.0Alpha1_20120808Marcel Ziswiler
2012-03-29Make u-boot recognize full range of PPT LPC controllersVadim Bendebury
The full range of LPC controllers should be accepted by u-boot when looking for the SPI controller. The values come from Intel's Panther_Point_EDS_v072.pdf (document #472178). BUG=chrome-os-partner:7734 TEST=manual . program the new image on the target . reboot it and observe coming up to ChromeOS login screen Change-Id: Id8f7068c3b48885f868a1f30e7927e678d2154b6 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/19147 Reviewed-by: Jon Salz <jsalz@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/19310 Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
2012-03-13gen: Make the SCSI command aware of READ CAPACITY (16) and how to use itGabe Black
The generic SCSI code in U-Boot was only aware of the READ CAPACITY (10) SCSI command which can detect the size of disks up to 2TB in size. If that size is exceeded, it should then try the READ CAPACITY (16) command which returns a 64 bit block count value. BUG=chrome-os-partner:8180 TEST=In conjunction with the next change, built and booted into ChromeOS on the Emerald Lake 2 CRB with a 250 GB SSD. Did the same but forced the READ CAPACITY (10) command to saturate and the code to fall back to READ CAPACITY (16). Note that this code has not be tested with a real SCSI disk, just the AHCI code pretending to be a SCSI disk as it historically has. Change-Id: Ia0ee3fa1264649f25065658d5d368101d39ce614 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/18060 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
2012-03-13x86: config: Turn on the CONFIG_SYS_64BIT_LBA option for corebootGabe Black
BUG=chrome-os-partner:8180 TEST=Built and booted on emeraldlake2 and Stumpy. Change-Id: If14ff4930015fae36d421fd30ab5bd126c464db9 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/18059 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
2012-02-27tegra: configs: enable warm boot on CardhuVarun Wadekar
enable CONFIG_TEGRA_LP0 and CONFIG_TEGRA3_WARMBOOT BUG=chromium-os:23496 TEST=build and boot on Cardhu Change-Id: If21303468193c7f5f6ba1c0c0b7cd0ccb5a08c0e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/13801
2012-02-27tegra: configs: enable warm boot on WaluigiVarun Wadekar
enable CONFIG_TEGRA_LP0 and CONFIG_TEGRA3_WARMBOOT BUG=chromium-os:23496 TEST=build and boot on Waluigi Change-Id: I622d228d02767954ffa7e101ad6f5f5fb1146702 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/13802
2012-02-27arm: tegra3: add warmboot code needed for LP0Varun Wadekar
BUG=chromium-os:23496 TEST=build and boot on Waluigi, Cardhu by enabling CONFIG_TEGRA_LP0 and CONFIG_TEGRA3_WARMBOOT. odification of the work done by: a. Jimmy Zhang <jimmzhang@nvidia.com> b. Yen Lin <yelin@nvidia.com> c. Wei Ni <wni@nvidia.com> Change-Id: If2fa63ccd23341694955bca25fb5cfc4a8a805ad Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/13800
2012-02-16arm: config: tegra: add bct offset addressVarun Wadekar
BUG=chromium-os:23496 TEST=build for Cardhu, Waluigi and Seaboard Change-Id: I32dbfa02ac1d6954b3a7e515914fbc0b6695f98b Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/14683
2012-02-14arm: tegra2: split LP0 code to help future chipsVarun Wadekar
split the LP0 code for tegra2 into common LP0 code and chip specific warm boot code BUG=chromium-os:23496 TEST=build for Seaboard Change-Id: Ie04bf9ac17482a37afd0f4515dc3aafeb4f48ae7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/15883
2012-02-08Revert "arm: tegra2: split LP0 code to help future chips"Brian Harring
This reverts commit 4c7502242627f64d91432cb4958be5f93f65fbff Don't think this is the cause of http://code.google.com/p/chromium-os/issues/detail?id=26116, but it was in the same batch so I'm reverting in the process. Change-Id: Icc013ced6c22e29d569ee4ca8ef73522154ec1a8 Reviewed-on: https://gerrit.chromium.org/gerrit/15561 Reviewed-by: Brian Harring <ferringb@chromium.org> Tested-by: Brian Harring <ferringb@chromium.org>
2012-02-08arm: tegra2: split LP0 code to help future chipsVarun Wadekar
split the LP0 code for tegra2 into common LP0 code and chip specific warm boot code BUG=chromium-os:23496 TEST=build for Seaboard Change-Id: Id9756c08f61502affa8beee636d883d01468e6ec Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/13799
2012-02-07tegra: Rename "CONFIG_VIDEO_TEGRA2" to "CONFIG_VIDEO_TEGRA"Puneet Saxena
Enables common LCD support for Tegra2 and Tegra3 BUG=chromium-os:23496 TEST=Built ok for Cardhu, Waluigi and Seaboard. Change-Id: I938824045440cc4964c2ac6bf727a90ee5f129b4 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/14692
2012-02-07arm: Tegra3: Add initrd ATAG support to all Tegra3Varun Wadekar
Helps kernel developers using kernels with custom ramdisk images. Some developers who would like to work with upstream kernel specifically requested for this feature, since it helps them during early development days. BUG=chromium-os:23496 TEST=build and boot on Cardhu, Waluigi Change-Id: I698da421bf924a5c86229a80c0a25021d3e6f046 Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/14475 Reviewed-by: Simon Glass <sjg@chromium.org> Commit-Ready: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
2012-02-07tegra: config: waluigi: Enable keyboard support for WaluigiPuneet Saxena
Add Keyboard config options CONFIG_TEGRA_KEYBOARD and CONFIG_KEYBOARD. BUG=chromium-os:23496 TEST=Tested on Waluigi. key press echoes the key on console. Build OK for cardhu. Change-Id: I7856f2d22c935a4a94f91c67263913e1240f25b5 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/13790 Commit-Ready: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
2012-02-06tegra: config: Rename CONFIG_TEGRA2_KEYBOARDPuneet Saxena
Replace Tegra2 specific tag "CONFIG_TEGRA2_KEYBOARD" by common tag "CONFIG_TEGRA_KEYBOARD" to include tegra keyboard driver. BUG=chromium-os:23496 TEST=Build ok for Cardhu,Seaboard and Waluigi. Change-Id: Idd16990ba525b8391c3c14e37efd5587f09a25c8 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/13860 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-02-05tegra: waluigi: enable LCD supportPuneet Saxena
BUG=chromium-os:23496 TEST=Built ok for Cardhu, Waluigi and Seaboard. Tested on Waluigi. Change-Id: Ifb4deba51137251ea0564bf3e66f33f7c62420e4 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/14701 Reviewed-by: Simon Glass <sjg@chromium.org>
2012-01-25AHCI: cosmetics and cleanupStefan Reinauer
- print the correct speed - print all the AHCI capability flags (information taken from Linux kernel driver) - clean up some comments Signed-off-by: Stefan Reinauer <reinauer@google.com> BUG=chrome-os-partner:7714 TEST=See the following string in bios_log: AHCI 0001.0300 32 slots 6 ports 6 Gbps 0x3 impl SATA mode Change-Id: Ib32dbeddd0714359948e2bec033b2ec7aabbdb10 Reviewed-on: https://gerrit.chromium.org/gerrit/14754 Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Ready: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2012-01-25vbexport: report correct number of scsi drivesStefan Reinauer
Right now our code makes the assumption that there always is one SCSI drive in the system (the AHCI attached SDD). However, this might not be the case. This patch prevents vboot from using an uninitialized disk entry when instead it should go into recovery mode. BUG=chrome-os-partner:7716 TEST=none Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I761bbb3c92a60d4205a217c7b025f699deed83b0 Reviewed-on: https://gerrit.chromium.org/gerrit/14753 Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Ready: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2012-01-19Enable frequency selection in VbExBeep().Bill Richardson
BUG=none TEST=manual In dev-mode, press "Ctrl-U" with no USB stick inserted. If "crossystem dev_boot_usb" is 0, you'll hear two 400Hz beeps. If "crossystem dev_boot_usb" is 1, you'll hear one 200Hz beep. Signed-off-by: Bill Richardson <wfrichar@google.com> Change-Id: Ifd45a067ec8b922863331f13f3f4525ef40f7346 Reviewed-on: https://gerrit.chromium.org/gerrit/14529 Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Commit-Ready: Bill Richardson <wfrichar@chromium.org>
2012-01-18Introduce arch_phys_memset which works like memset but on physical memoryGabe Black
The default implementation of this function is just memset, but other implementations will be needed when physical memory isn't accessible by U-Boot using normal addressing mechanisms. BUG=chrome-os-partner:7579 TEST=From the original, larger patch: Built and booted on Lumpy, Stumpy, and Kaen. Looked at the log to see that the regions in high memory are listed as cleared. Artificially injected a range to "clear" with 0xA5 and then 0x5A which was over the framebuffer and covered part or all of the screen on Lumpy. Verified that the screen was partially or completely filled with an appropriate looking color. Had U-Boot print the PDTs it was generating to verify that the high address bits were preserved. Identity mapped only some of memory and verified that things that should be mapped were accessible and things that shouldn't be weren't. Signed-off-by: Gabe Black <gabeblack@google.com> Change-Id: Ie1ba5bbb8ee2847f450d0057611deee397c316cf Reviewed-on: https://gerrit.chromium.org/gerrit/14417 Reviewed-by: Gabe Black (Do Not Use) <gabeblack@google.com> Tested-by: Gabe Black (Do Not Use) <gabeblack@google.com>
2012-01-18configs: waluigi: remove pmuboard kernel argPuneet Saxena
BUG=chromium-os:23496 TEST=Build ok for Waluigi,Cardhu and Seaboard. "printenv bootargs" shows the changed kernel arg on Waluigi. Change-Id: I87934f9a887c367098152ac753f98681760ec160 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/13797 Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Commit-Ready: Che-Liang Chiou <clchiou@chromium.org> Tested-by: Olof Johansson <olofj@chromium.org>
2012-01-17Add generation of ANSI 3.64 escape sequences.Terry Lambert
This adds support for generation of ANSI 3.64 escape sequences to the PS/2 keyboard driver. This change significantly refactors the code: o It adds an FSA to support 0xE0 and 0xE1 multibyte PS/2 scan code sequences. o It converts the PS/2 scan codes to USB scan code values to facilitate sharing upper level code in future changes. Reasons to use USB scan codes: o Standard o Simple conversion to ASCII / ANSI 3.64 o Ability to share complex processing / state code o Shared international keymaps in higher level code o It adds an ANSI 3.64 escape sequence generator for USB special keys; the intent of doing this is to allow the transparent use of PS/2, USB, and network or serial devices using the same upper level u-boot clients. o It adds an input FIFO which is an almost verbatim copy of the Tegra matrix keyboard driver; future changes are expected to share the FIFOcode among all keyboard drivers. International keyboard support is expected to be handled at a higher layer in the future, using a much smaller NRCS (National Replacement Character Set) table instead of a duplicat table. Combined, the changes reduce the overall source file size by about 5K, and removes about 4K from the data segment as well. Note: Use of typedef for FSA states allows compiler to prohibit switch statement without default case from omitting states. BUG=chrome-os-partner:6580 TEST=Removed backslash from generated 3.64 sequences, stopped boot at command line, verified character sequence generation. Signed-off-by: tlambert@chromium.org Change-Id: I00200c5ccefd44679335fb643b21794e5d77663a modified: drivers/input/i8042.c modified: include/i8042.h Change-Id: I22c692f7bd65da5848908fc71c6cd7d04753f135 Reviewed-on: https://gerrit.chromium.org/gerrit/14218 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Gabe Black (Do Not Use) <gabeblack@google.com> Tested-by: Terry Lambert <tlambert@chromium.org> Commit-Ready: Terry Lambert <tlambert@chromium.org>
2012-01-13Coreboot: Compile out disk partition and file system codeGabe Black
The code which provides GPT support has some potential security issues in it. Since we're not using it anyway, we might as well just turn it off. BUG=chromium-os:25041 BUG=chromium-os:25042 TEST=Built and booted on Lumpy with various options turned on and off. Signed-off-by: Gabe Black <gabeblack@google.com> Change-Id: I7618ba1a34e553094c1cd96bfe892c9c6d0f02ba Reviewed-on: https://gerrit.chromium.org/gerrit/14180 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org>
2012-01-13Make the memory wipe code handle 64 bit addresses properlyGabe Black
When telling the memory wipe infrastructure about regions it should and shouldn't wipe, some of those addresses may be 64 bits on x86. This change makes the infrastructure pass around those addresses intact instead of truncating them, and then simply ignore the regions that are unaddressable by U-Boot. BUG=None TEST=Built and booted on Lumpy. Built on Kaen Signed-off-by: Gabe Black <gabeblack@google.com> Change-Id: I657cd5480ca9a33614b032bf2a727d1a74d38b48 Reviewed-on: https://gerrit.chromium.org/gerrit/14149 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Commit-Ready: Gabe Black (Do Not Use) <gabeblack@google.com> Tested-by: Gabe Black (Do Not Use) <gabeblack@google.com>
2012-01-13config: coreboot: allow to unregister input devicesVincent Palatin
Allow to reconfigure properly the USB keyboard driver when we enumerate several times the USB devices and its position in the device tree has changes. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:7188 chrome-os-partner:7430 chrome-os-partner:7432 chrome-os-partner:7559 TEST=On lumpy with usb keyboard configured, run in recovery mode, insert a bad key, press tab, remove the key, press tab. The recovery info are displayed properly. Change-Id: Ief5e25879fe75fb6371a089a310c5d6af662252f Reviewed-on: https://gerrit.chromium.org/gerrit/14188 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
2012-01-13stdio: fix stack memory corruptionVincent Palatin
When copying the device name, the temporary target variable was twice smaller than the copy size. Create a define to ensure this won't break again. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:7188 chrome-os-partner:7430 chrome-os-partner:7432 chrome-os-partner:7559 TEST=On lumpy with usb keyboard configured, run in recovery mode, insert a bad key, press tab, remove the key, press tab. The recovery info are displayed properly. Change-Id: Ia9e765555d2f4efba81b8c389be2778cf2b92db0 Reviewed-on: https://gerrit.chromium.org/gerrit/14185 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
2012-01-11CHROMIUM: x86: Add entry in ACPI NVS table for the ME hashDuncan Laurie
BUG=chromium-os:24151 TEST=verify ME hash in the OS Change-Id: I752bdb9e7fedc3a25772ba33b00d981b9e3db4b0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/13994 Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
2012-01-06Fix u-boot on x86Stefan Reinauer
This fixes the breakage introduced by https://gerrit.chromium.org/gerrit/#change,13371 BUG=none TEST=emerge-stumpy chromeos-u-boot does not fail anymore Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: If969ea2aab6a29d6c22053a63ef1b155d3fb42fa Reviewed-on: https://gerrit.chromium.org/gerrit/13842 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Commit-Ready: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2012-01-05Track lcd wait time using bootstageSimon Glass
The intent is for LCD init to happen such that we never need to call udelay(). Add tracking that this is indeed the case, and report it with the boot time report. BUG=chromium-os:22938 TEST=build and boot on Kaen Change-Id: I78e458a6b878a4237e4e059525bae4fa47844ed9 Reviewed-on: https://gerrit.chromium.org/gerrit/13377 Commit-Ready: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2012-01-05Add bootstage timing to TPM operationsSimon Glass
Records the total time taken by TPM operations for display as part of the bootstage report. BUG=chromium-os:22938 TEST=build and boot on Kaen Change-Id: I7ce6efa3c2bb90858d17ab6613724e6ae73d918b Reviewed-on: https://gerrit.chromium.org/gerrit/13371 Commit-Ready: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2012-01-05Add bootstage accumulationSimon Glass
This adds a new type of boot timer, which records the time taken by an operation, rather than marking the instant when it occurred. This is useful to track the amount of time spent in a repeating activity during boot. To use this, call bootstage_start() at the start of the activity, then bootstage_accum() at the end, to add this segment of time to the total. You can call them (start first, then accum) as many times as you like. BUG=chromium-os:22938 TEST=build and boot on Kaen Change-Id: I3f1b536dc140c91a4a780188f6974dc37780f4f0 Reviewed-on: https://gerrit.chromium.org/gerrit/13370 Commit-Ready: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2012-01-05Add option to tftp kernel then boot from eMMCSimon Glass
The mmc0_tftpboot option reads a kernel using TFTP but then boots from eMMC. This allows kernel development without resorting to NFS root (which changes some parts of the boot process). BUG=chromium-os:22938 TEST=build and boot on Kaen Change-Id: I23c0890f76dc63dde128d7137d8891341761c884 Reviewed-on: https://gerrit.chromium.org/gerrit/13280 Commit-Ready: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2012-01-05CHROMIUM: config: Skip LCD final init for secure bootSimon Glass
The vboot command makes sure that the LCD init is completed so we don't need this in board_late_init(). Overall the LCD init optimization reduces boot time by about 150ms. BUG=chromium-os:22938 TEST=build and boot on Kaen Change-Id: Idcefb81108d0499bb208f8b3d90df65ca4cb6349 Reviewed-on: https://gerrit.chromium.org/gerrit/13206 Commit-Ready: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2012-01-05tegra: config: Enable BOARD_LATE_INIT to complete LCD initSimon Glass
LCD final init is now kept in board_late_init(), so we need to enable this feature in the config. BUG=chromium-os:22938 TEST=build and boot on Kaen Change-Id: Ib895c2768359439349714805cea6ff636c2307b3 Reviewed-on: https://gerrit.chromium.org/gerrit/13214 Commit-Ready: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2012-01-05usb: increase timeout on the control endpointVincent Palatin
Some USB keys are very slow at answering the initial GET_DESCRIPTOR or SET_ADDRESS request. I have encountered a couple of USB keys which take respectively 140ms and 230ms to send back their data packet on such a request, and thus fail with the current code. According to the USB2.0 standard 9.2.6.4, the device should answer the standard device requests (e.g. GET_DESCRIPTOR or SET_ADDRESS) in less than 500ms, so let's increase the control endpoint timeout to that value. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:7344 chrome-os-partner:7345 TEST=boot a recovery image from the 2 previously non working keys. (Lexar JUMPDRIVE TwistTurn LJDTT32GASBNA and USB M316 Aquarium Tutle) Change-Id: I00ffb11810ac538bae4622ecba7edd2388d592b2 Reviewed-on: https://gerrit.chromium.org/gerrit/13716 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
2012-01-04Do not use CONTROL_EP method of getting USB keyboard eventsPatrick Georgi
The GetReport request isn't implemented in all keyboards, so use interrupt transfers instead. BUG=chrome-os-partner:5752 TEST=Use USB keyboard in u-boot (recovery mode) Change-Id: Ided3289ef86ee9899813582c9f137526399ad2f8 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: https://gerrit.chromium.org/gerrit/13491 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
2011-12-21CHROMIUM: config: delay console init until after relocationSimon Glass
Turning on this option saves about 20ms boot time. BUG=chromium-os:22938 TEST=build and boot on Kaen Change-Id: I06ec0ae0da4afc208ca7952dfa42e725f5a67d4c Reviewed-on: https://gerrit.chromium.org/gerrit/13208 Commit-Ready: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-12-21Add CONFIG_DELAY_CONSOLE to delay console initSimon Glass
This option delays console initialization until after relocation. This can save time if this init is relatively expensive, since after relocation the CPU is often running much faster. This option should be used in conjunction with CONFIG_PRE_CONSOLE_BUFFER to ensure that all console output is buffered until the console is ready for it. This saves about 30ms boot time. BUG=chromium-os:22938 TEST=build and boot on Kaen Change-Id: I3a774b418d45e7be9338f9942df445c2c2baa528 Reviewed-on: https://gerrit.chromium.org/gerrit/13207 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Tom Wai-Hong Tam <waihong@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Commit-Ready: Simon Glass <sjg@chromium.org>
2011-12-20Security: Make sure not to overflow the in memory version of the GBBGabe Black
This is a revised version of this patch which fixes an ARM bug. This change plumbs the size of the GBB specified in the device tree to the functions that read it from the flash into memory, and adds checks to those functions to make sure they don't spill out of the in memory GBB. From a security standpoint this is a largely theoretical problem since the GBB is in the read only portion of flash and if that can be modified the machine is totally compromised, but it's possible somehow an attacker could force vboot to read the GBB from the wrong place. From a practical perspective it's not a bad idea to check this to avoid accidental memory corruption. BUG=chromium-os:24223 TEST=Built and booted on Lumpy. Built for Kaen. Change-Id: I90d23fd6e055db595af12b1bd63d9932cbffe7ae Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/13279 Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org>
2011-12-20Revert "Security: Make sure not to overflow the in memory version of the GBB"Simon Glass
This breaks recovery mode on Kaen - the bitmaps are not displayed. This reverts commit e1153e1f56ebebff188f3693e534f10bd68e6f07 Change-Id: I300ae39382dc1960bb0375ad660a88b65181edc9 Reviewed-on: https://gerrit.chromium.org/gerrit/13274 Reviewed-by: Gabe Black (Do Not Use) <gabeblack@google.com> Commit-Ready: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-12-20USB: add device connection/disconnection detectionVincent Palatin
Provide a function to detect USB device insertion/removal in order to avoid having to do USB enumeration in a tight loop when trying to detect peripheral hotplugging. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:5752 chrome-os-partner:6344 TEST=on Lumpy, insert and remove a USB key in recovery mode. Change-Id: I18dc97d54cd909acea754fd9b3a4b7f4fc3219ec Reviewed-on: https://gerrit.chromium.org/gerrit/13249 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org>
2011-12-20Add a new boot stage to time relocationSimon Glass
Relocation takes about 40ms of the boot time, so add a timer to track it. BUG=chromium-os:22938 TEST=build and boot on Kaen Change-Id: If936bc8ff9a23f6dd885f60e845a597ac7edad97 Reviewed-on: https://gerrit.chromium.org/gerrit/13203 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Commit-Ready: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-12-20Security: Make sure not to overflow the in memory version of the GBBGabe Black
This change plumbs the size of the GBB specified in the device tree to the functions that read it from the flash into memory, and adds checks to those functions to make sure they don't spill out of the in memory GBB. From a security standpoint this is a largely theoretical problem since the GBB is in the read only portion of flash and if that can be modified the machine is totally compromised, but it's possible somehow an attacker could force vboot to read the GBB from the wrong place. From a practical perspective it's not a bad idea to check this to avoid accidental memory corruption. BUG=chromium-os:24223 TEST=Built and booted on Lumpy. Built for Kaen. Change-Id: I4f33552f9d27321e73659520b08be52d775a6a9b Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/13228 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org>
2011-12-16Add beep for x86 chormeos.Dylan Reid
Implement the VbExBeep function so that the DEV screen can beep. Much of this code was coppied from coreboot. BUG=chrome-os-partner:7114 TEST=manual, check that Stumpy beeps on DEV screen timeout and when booting from USB with dev_boot_usb=0. Change-Id: Icd4eabb0b10cc3d226db71e6a2b52d3ed7eb25ef Signed-off-by: Dylan Reid <dgreid@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/13110 Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
2011-12-16For ChromeOS systems, don't show coreboot as BIOS vendor/versionStefan Reinauer
Instead, once we know which firmware we are actually running on, copy the FWID to the BIOS version in the SMBIOS table. BUG=chrome-os-partner:6827 TEST=Boot Stumpy, go to chrome://settings/about and see Google_Stumpy.... show up as "Firmware" Signed-off-by: Stefan Reinauer <reinauer@google.com> Also needs https://gerrit-int.chromium.org/#change,9288 Change-Id: I2e16a2fdb7fb835b0a0fbf08462d8a98b3cfe208 Reviewed-on: https://gerrit.chromium.org/gerrit/13098 Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2011-12-15Don't use bogus gbb address when booting up rewriteable firmware.Vadim Bendebury
https://gerrit.chromium.org/gerrit/11152 introduced a bug where the gbb pointer used during rewriteable firmware boot is bogus. The pointer is retrieved from the 'chromeos-config' section of the device tree, but on x86 platform this memory area is never initialized. The fix is to make sure that the proper gbb address in the CPU address space is used before gbb contents are accessed. What it boils down to is that when CONFIG_HARDWARE_MAPPED_SPI is set, gbb address should be determined before setup_gbb_and_cdata() is called. To accomplish that fdt_decode_twostop_fmap() is being modified to retrieve the flash base address among other things. Calling this function before setup_gbb_and_cdata() allows to assign the gbb pointer before it is used. `google-binary-block' is not yet being removed from the cromeos-config section of the device tree as this could break some tests. BUG=chromium-os:22528 BUG=chrome-os-partner:7155 TEST=manual . build a new firmware image and program it on a Lumpy . verify that the device comes up as expected . modify the firmware to use read/write path as suggested by hungte@ cd ~/trunk/src/platform/vboot_reference/scripts/image_signing ./resign_firmwarefd.sh /build/lumpy/firmware/image.bin \ /build/lumpy/firmware/new_image.bin \ ../../tests/devkeys/firmware_data_key.vbprivk \ ../../tests/devkeys/firmware.keyblock \ ../../tests/devkeys/firmware_data_key.vbprivk \ ../../tests/devkeys/firmware.keyblock \ ../../tests/devkeys/kernel_subkey.vbpubk \ 1 0 . put new_image.bin into a lumpy flashrom . reboot the device . observe it come up, printing on the console 'vboot_twostop: jump to readwrite main firmware at 0x1110000, size 0xdffc0' along the way Change-Id: Ieeaadafdf31ee6199a6f1fce0b9684dd494a7602 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/12969 Reviewed-by: Simon Glass <sjg@chromium.org>
2011-12-14Tegra3: Cardhu: Fix Cardhu buildTom Warren
BUG=chromium-os:23496 TEST=built and booted Cardhu to cmd prompt; USB, MMC, SPI all work. This build is to allow developers that don't have a Waluigi to still contribute to porting/upstreaming T30 U-Boot code/patches. Signed-off-by: Tom Warren <twarren@nvidia.com> Change-Id: I5978cbe33bfc9329f420c32eb5ca97b9b302029c Reviewed-on: https://gerrit.chromium.org/gerrit/12932 Reviewed-by: Simon Glass <sjg@chromium.org>
2011-12-13arm: Tegra3: enable USB supportTom Warren
BUG=chromium-os:23496 TEST=build and boot Waluigi T30. Usb detects devices OK. usb tree, usb part, ext2ls usb and ext2load usb work as expected. Signed-off-by: Tom Warren <twarren@nvidia.com> Change-Id: I40910e0c770bb33171ad9c8b4e5a6baaaac4a7df Reviewed-on: https://gerrit.chromium.org/gerrit/12392 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Commit-Ready: Simon Glass <sjg@chromium.org>
2011-12-12CHROMIUM: Make config names consistentChe-Liang Chiou
In making config names consistent, this commit renames configs following the "chromeos_${BOARD}" naming convention. The old config names are kept before portage overlays are set to the new config names to prevent builders from break. They will be removed in next commit. BUG=chromium-os:23869 TEST=Run script snippet below successfully >>>> for BOARD in lumpy \ stumpy \ tegra2_aebl \ tegra2_arthur \ tegra2_asymptote \ tegra2_dev-board \ tegra2_dev-board-opengl \ tegra2_kaen \ tegra2_seaboard \ tegra2_wario \ waluigi \ x86-alex \ x86-alex_he \ x86-mario \ x86-mario64 do ebuild-${BOARD} /path/to/chromeos-u-boot-9999.ebuild configure done <<<< Change-Id: I984bea648f6d8384facce9771a7a5de3b169108c Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/12671 Reviewed-by: Simon Glass <sjg@chromium.org>
2011-12-12tegra: Remove CONFIG_SYS_PLLP_BASE_IS_408MHZSimon Glass
This setting is now in the fdt, so remove the CONFIG item. BUG=chromium-os:23496 TEST=build and boot on Seaboard, T33, Kaen Change-Id: I336a6cc2140c725fdda85330efe617f82f205a90 Reviewed-on: https://gerrit.chromium.org/gerrit/12250 Commit-Ready: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
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