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We use upper case letters for the AMCC processor defines (like
CONFIG_440SPE) in U-Boot. So the 440SPe is labeled CONFIG_440SPE and
not CONFIG_440SPe. This patch fixes the last misspelled config options.
Signed-off-by: Stefan Roese <sr@denx.de>
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This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).
Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.
Signed-off-by: Wolfgang Denk <wd@denx.de>
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Signed-off-by: Ilya Yanok <yanok@emcraft.com>
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Don't run futher tests in case of a test fails that is marked as
POST_STOP.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
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Added OCM test to POST layer. This version runs before all other tests
but doesn't yet interrupt post sequence on failure.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
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Signed-off-by: Ilya Yanok <yanok@emcraft.com>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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Update ChNAGELOG, minor white space cleanup.
Signed-off-by: Wolfgang Denk <wd@denx.de>
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Signed-off-by: Sascha Laue <sascha.laue@liebherr.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
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Signed-off-by: Sascha Laue <sascha.laue@liebherr.com>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
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The specification for the lwmon5 board dsPIC POST got changed.
Also add defines for the temperatures and voltages.
Signed-off-by: Sascha Laue <sascha.laue@liebherr.com>
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If the hardware watchdog detects a voltage error, the watchdog sets
GPIO62 to low. The watchdog POST has to detect this low level.
Signed-off-by: Sascha Laue <leglas0@legpc180.leg.liebherr.i>
Signed-off-by: Wolfgang Denk <wd@denx.de>
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Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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ARFLAGS was not set, which caused "ppc_8xx-ar: creating libgenpost.a"
messages to be printed.
Signed-off-by: Wolfgang Denk <wd@denx.de>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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Conflicts:
common/cmd_bootm.c
common/cmd_log.c
include/common.h
post/board/lwmon5/Makefile
post/board/lwmon5/dsp.c
post/board/lwmon5/dspic.c
post/board/lwmon5/fpga.c
post/board/lwmon5/gdc.c
post/board/lwmon5/sysmon.c
post/board/lwmon5/watchdog.c
Signed-off-by: Wolfgang Denk <wd@denx.de>
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Introduce the new logical option CONFIG_HAS_POST which is set when the
platform has CONFIG_POST set. Use CONFIG_HAS_POST in the post/ Makefiles
to determine should the POST libs be compiled for the selected target
platform, or not.
To avoid breaking u-boot linking process, the empty post/libpost.a file is
created for platforms which do not have POSTs.
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
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Remove CONFIG_POST ifdefs from the post/ source files.
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
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If the hardware watchdog detects a voltage error, the watchdog sets
GPIO62 to low. The watchdog POST has to detect this low level.
Signed-off-by: Sascha Laue <leglas0@legpc180.leg.liebherr.i>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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Fix errors in the LWMON5 Sysmon POST for negative temperatures.
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
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Add test for DPIC_SYS_ERROR_REG to be zero in the LWMON5 dsPIC POST.
Signed-off-by: Yuri Tikhonov <yur@emcraft.com> ---
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plus some coding style cleanup
Signed-off-by: Wolfgang Denk <wd@denx.de>
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Modify the RTC API to provide one a status for the time reported by
the rtc_get() function:
0 - a reliable time is guaranteed,
< 0 - a reliable time isn't guaranteed (power fault, clock issues,
and so on).
The RTC chip drivers are responsible for providing this info if the
corresponding chip supports such functionality. If not - always
report that the time is reliable.
The POST RTC test was modified to detect the RTC faults utilizing
this new rtc_get() feature.
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
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Signed-off-by: Dmitry Rakhchev <rda@emcraft.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
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Backlight was switched on even when temperature was too low.
Signed-off-by: Dmitry Rakhchev <rda@emcraft.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
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watch-dog for now.
Signed-off-by: Dmitry Rakhchev <rda@emcraft.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
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as POST_CRITICAL fails then the alternative, post_critical, boot-command is used. If this command is not defined then U-Boot enters into interactive mode.
Signed-off-by: Dmitry Rakhchev <rda@emcraft.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
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* External Watchdog test;
* dsPIC tests;
* FPGA test;
* GDC test;
* Sysmon tests.
Signed-off-by: Dmitry Rakhchev <rda@emcraft.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
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Signed-off-by: Dmitry Rakhchev <rda@emcraft.com>
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Signed-off-by: Dmitry Rakhchev <rda@emcraft.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
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Backlight was switcehd on even when temperature was too low.
Signed-off-by: Dmitry Rakhchev <rda@emcraft.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
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Disable external watch-dog for now.
Signed-off-by: Dmitry Rakhchev <rda@emcraft.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
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marked as POST_CRITICAL fails then the alternative, post_critical,
boot-command is used. If this command is not defined then U-Boot
enters into interactive mode.
Signed-off-by: Dmitry Rakhchev <rda@emcraft.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
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These are:
* External Watchdog test;
* dsPIC tests;
* FPGA test;
* GDC test;
* Sysmon tests.
Signed-off-by: Dmitry Rakhchev <rda@emcraft.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
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Signed-off-by: Dmitry Rakhchev <rda@emcraft.com>
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This patch changes the physical addess parameter from 32bit to 64bit.
This is needed for 36bit 4xx platforms to access areas located
beyond the 4GB border, like SoC peripherals (EBC etc.).
Signed-off-by: Stefan Roese <sr@denx.de>
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Fix warnings while compilation with new gcc in eldk-4.2
Signed-off-by: Anatolij Gustschin <agust@denx.de>
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Currently (since commit b2e2142c) u-boot crashes on
sequoia board while SPR test if CONFIG_4xx_DCACHE is
enabled. This patch disables the cache while SPR test.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
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The CPU POST test code (run from cpu_post_exec_31()) doesn't follow the
ABI carefully, at least the CR3, CR4, and CR5 fields of CR are clobbered
by it. The gcc-4.2 with its more aggressive optimization exposes this fact.
This patch just saves the CR value before running the test code, so allowing
it to do anything it wants with CR.
Signed-off-by: Dmitry Rakhchev <rda@emcraft.com>
Acked-by: Yuri Tikhonov <yur@emcraft.com>
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Signed-off-by: Larry Johnson <lrj@acm.org>
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The ECC POST reported intermittent failures running after power-up on
the Korat PPC440EPx board. Even when the test passed, the debugging
output occasionally reported additional unexpected ECC errors.
This refactoring has three main objectives: (1) minimize the code
executed with ECC enabled during the tests, (2) add more checking of the
results so any unexpected ECC errors would cause the test to fail, and
(3) use synchronization (only) where required by the processor.
Signed-off-by: Larry Johnson <lrj@acm.org>
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post/cpu/ppc4xx/spr.c contained a few checks for registers only present
for PPC440 and derivates processor.
Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
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On LWMON5 we now use d-cache as init-ram and stack. The SPR POST test uses
self modifying code and this doesn't work with stack in d-cache, since
I can't move the code from d-cache to i-cache. We move the SPR test to
be executed a little later, after relocation. Then stack is located in
SDRAM and this self-modifying code is no problem anymore.
Signed-off-by: Stefan Roese <sr@denx.de>
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