From 4a9de565a3f1de5afdd615e649665c4b7541466b Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 16 Oct 2015 11:28:17 +0200 Subject: apalis/colibri_imx6: cosmetic board file changes Fix various comment style, indentation and spelling issues in our Apalis/Colibri iMX6 board files. --- board/toradex/apalis_imx6/apalis_imx6.c | 31 ++++++++++++++------------ board/toradex/colibri_imx6/colibri_imx6.c | 36 +++++++++++++++++-------------- 2 files changed, 37 insertions(+), 30 deletions(-) diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c index 7546e19848..6232e2f9bd 100644 --- a/board/toradex/apalis_imx6/apalis_imx6.c +++ b/board/toradex/apalis_imx6/apalis_imx6.c @@ -113,7 +113,7 @@ struct i2c_pads_info i2c_pad_info1 = { } }; -/* Apalis local, PMIC, SGTL5000, STMPE811*/ +/* Apalis local, PMIC, SGTL5000, STMPE811 */ struct i2c_pads_info i2c_pad_info_loc = { .scl = { .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, @@ -203,7 +203,7 @@ int mx6_rgmii_rework(struct phy_device *phydev) /* * Bug: Apparently Apalis iMX6 does not works with Gigabit switches... * Limiting speed to 10/100Mbps, and setting master mode, seems to - * be the only way to have a successfull PHY auto negotiation. + * be the only way to have a successful PHY auto negotiation. * How to fix: Understand why Linux kernel do not have this issue. */ phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00); @@ -263,7 +263,7 @@ static int reset_enet_phy (struct mii_dev *bus) return 0; } -/* mux the Apalis GPIO pins to gpio, so they can be used from the U-Boot commandline */ +/* mux the Apalis GPIO pins to GPIO, so they can be used from the U-Boot commandline */ iomux_v3_cfg_t const gpio_pads[] = { MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), /* Apalis GPIO1 */ MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(WEAK_PULLUP), /* Apalis GPIO2 */ @@ -296,7 +296,8 @@ iomux_v3_cfg_t const usb_pads[] = { # define GPIO_USBO_EN IMX_GPIO_NR(3, 22) }; -/* if UARTs are used in DTE mode, switch the mode on all UARTs before +/* + * If UARTs are used in DTE mode, switch the mode on all UARTs before * any pinmuxing connects a (DCE) output to a transceiver output. */ #define UFCR 0x90 /* FIFO Control Register */ @@ -450,14 +451,14 @@ int board_eth_init(bd_t *bis) if (!bus) return 0; bus->reset = reset_enet_phy; - /* scan phy 4,5,6,7 */ + /* scan PHY 4,5,6,7 */ phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); if (!phydev) { free(bus); - puts("no phy found\n"); + puts("no PHY found\n"); return 0; } - printf("using phy at %d\n", phydev->addr); + printf("using PHY at %d\n", phydev->addr); ret = fec_probe(bis, -1, base, bus, phydev); if (ret) { printf("FEC MXC: %s:failed\n", __func__); @@ -480,7 +481,7 @@ static iomux_v3_cfg_t const backlight_pads[] = { /* PWM4 pin */ MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10) - /* buffer output enable 0: buffer enabled*/ + /* buffer output enable 0: buffer enabled */ MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP), #define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2) /* PSAVE# integrated VDAC */ @@ -489,8 +490,10 @@ static iomux_v3_cfg_t const backlight_pads[] = { }; static iomux_v3_cfg_t const pwr_intb_pads[] = { - /* the bootrom sets the iomux to vselect, potentially connecting - * two outputs. Set this back to GPIO */ + /* + * the bootrom sets the iomux to vselect, potentially connecting + * two outputs. Set this back to GPIO + */ MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL) }; @@ -527,7 +530,7 @@ static iomux_v3_cfg_t const rgb_pads[] = { static iomux_v3_cfg_t const vga_pads[] = { #ifdef FOR_DL_SOLO - /* Dualite/Solo doesn't have IPU2 */ + /* DualLite/Solo doesn't have IPU2 */ MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, @@ -774,7 +777,7 @@ static void setup_display(void) <gpr[3]); - /* backlights unconditionally on for now */ + /* backlight unconditionally on for now */ imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); /* use 0 for EDT 7", use 1 for LG fullHD panel */ @@ -876,10 +879,10 @@ int checkboard_fallback(void) #ifdef CONFIG_CMD_BMODE static const struct boot_mode board_boot_modes[] = { - /* 4 bit bus width */ + /* 4-bit bus width */ {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, {"sd", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, - {NULL, 0}, + {NULL, 0}, }; #endif diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index 50d1d1f7b6..ecd8956acb 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -107,7 +107,7 @@ struct i2c_pads_info i2c_pad_info1 = { } }; -/* Colibri local, PMIC, SGTL5000, STMPE811*/ +/* Colibri local, PMIC, SGTL5000, STMPE811 */ struct i2c_pads_info i2c_pad_info_loc = { .scl = { .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, @@ -166,7 +166,7 @@ static void setup_iomux_enet(void) imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); } -/* mux auxilary pins to gpio, so they can be used from the U-Boot commandline */ +/* mux auxiliary pins to GPIO, so they can be used from the U-Boot commandline */ iomux_v3_cfg_t const gpio_pads[] = { /* ADDRESS[17:18] [25] used as GPIO */ MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), @@ -256,7 +256,8 @@ iomux_v3_cfg_t const usb_pads[] = { #endif }; -/* UARTs are used in DTE mode, switch the mode on all UARTs before +/* + * UARTs are used in DTE mode, switch the mode on all UARTs before * any pinmuxing connects a (DCE) output to a transceiver output. */ #define UFCR 0x90 /* FIFO Control Register */ @@ -375,7 +376,7 @@ int board_eth_init(bd_t *bis) struct phy_device *phydev = NULL; int ret; - //provide the phy clock from the i.mx6 + /* provide the PHY clock from the i.MX 6 */ ret = enable_fec_anatop_clock(ENET_50MHZ); if (ret) return ret; @@ -388,14 +389,14 @@ int board_eth_init(bd_t *bis) bus = fec_get_miibus(base, -1); if (!bus) return 0; - /* scan phy 1..7 */ + /* scan PHY 1..7 */ phydev = phy_find_by_mask(bus, 0xff, PHY_INTERFACE_MODE_RMII); if (!phydev) { free(bus); - puts("no phy found\n"); + puts("no PHY found\n"); return 0; } - printf("using phy at %d\n", phydev->addr); + printf("using PHY at %d\n", phydev->addr); ret = fec_probe(bis, -1, base, bus, phydev); if (ret) { printf("FEC MXC: %s:failed\n", __func__); @@ -407,8 +408,10 @@ int board_eth_init(bd_t *bis) } static iomux_v3_cfg_t const pwr_intb_pads[] = { - /* the bootrom sets the iomux to vselect, potentially connecting - * two outputs. Set this back to GPIO */ + /* + * the bootrom sets the iomux to vselect, potentially connecting + * two outputs. Set this back to GPIO + */ MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL) }; @@ -580,7 +583,7 @@ static void setup_display(void) <gpr[3]); - /* backlights unconditionally on for now */ + /* backlight unconditionally on for now */ imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); /* use 0 for EDT 7", use 1 for LG fullHD panel */ @@ -656,8 +659,8 @@ int checkboard_fallback(void) #ifdef CONFIG_CMD_BMODE static const struct boot_mode board_boot_modes[] = { - {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, - {NULL, 0}, + {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, + {NULL, 0}, }; #endif @@ -669,11 +672,12 @@ int misc_init_r(void) return 0; } -/* On Colibri iMX6 the DDR bus width depends on the CPU type - * With Solo it is 32bit, with Dual Light 64 bit. - * U-Boot is configured to use 32bit on both models which works. +/* + * On Colibri iMX6 the DDR bus width depends on the CPU type + * With Solo it is 32-bit, with DualLite 64-bit. + * U-Boot is configured to use 32-bit on both models which works. * This commands patches this so that on subsequent boots a DL - * will use 64bit and thus all stuffed memory + * will use 64-bit and thus all stuffed memory. */ int do_patch_ddr_size(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -- cgit v1.2.3