From f85d97b26c8773d6261f0db76278cdc01a698130 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 15 Jun 2025 12:51:07 +0200 Subject: arm64: renesas: Convert SCIF SREC from u-boot-spl.bin Convert u-boot-spl.bin instead of u-boot-spl ELF into SCIF loader compatible SREC. The u-boot-spl.bin includes SPL DT, while the ELF does not, which leads to failure to start SPL via SCIF loader due to missing SPL DT. Fix this by using u-boot-spl.bin which includes the DT. Signed-off-by: Marek Vasut --- arch/arm/mach-renesas/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-renesas/Makefile b/arch/arm/mach-renesas/Makefile index 317fce02d2b..3409437d75a 100644 --- a/arch/arm/mach-renesas/Makefile +++ b/arch/arm/mach-renesas/Makefile @@ -19,12 +19,12 @@ ifneq ($(CONFIG_RCAR_64),) obj-$(CONFIG_ARMV8_PSCI) += psci-rcar64.o endif -OBJCOPYFLAGS_u-boot-spl.srec := -O srec +OBJCOPYFLAGS_u-boot-spl.srec := -I binary -O srec --change-addresses=$(CONFIG_SPL_TEXT_BASE) quiet_cmd_objcopy = OBJCOPY $@ cmd_objcopy = $(OBJCOPY) --gap-fill=0x00 $(OBJCOPYFLAGS) \ $(OBJCOPYFLAGS_$(@F)) $< $@ -spl/u-boot-spl.srec: spl/u-boot-spl FORCE +spl/u-boot-spl.srec: spl/u-boot-spl.bin FORCE $(call if_changed,objcopy) srec_cat_gte_160 := ${shell expr `srec_cat -VERSION | grep ^srec_cat | sed 's/^.* //g' | cut -f1-2 -d.` \>= "1.60"} -- cgit v1.2.3 From 26758c24b913e54ca521f782fbf1c52dd4ee540e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 15 Jun 2025 12:51:08 +0200 Subject: arm64: renesas: Add Renesas R-Car Gen4 SCIF/HSCIF loader SREC generation Add Renesas R-Car Gen4 SCIF/HSCIF loader compatible SREC generation. This is a regular U-Boot SPL SREC augmented with a short header which describes where to store the received data and how much data to store. This header is interpreted by the R-Car Gen4 BootROM SCIF/HSCIF loader. Signed-off-by: Marek Vasut --- arch/arm/mach-renesas/Makefile | 10 ++++++++++ common/spl/Kconfig | 2 +- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-renesas/Makefile b/arch/arm/mach-renesas/Makefile index 3409437d75a..9165ceab4a3 100644 --- a/arch/arm/mach-renesas/Makefile +++ b/arch/arm/mach-renesas/Makefile @@ -34,6 +34,15 @@ else srec_cat_le_cmd := "-l-e-constant" endif +ifneq ($(CONFIG_RCAR_GEN4),) +quiet_cmd_srec_cat = SRECCAT $@ + cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \ + -Output_Block_Size 16 \ + -generate 0xeb203000 0xeb203154 $(srec_cat_le_cmd) 0x0 4 \ + -generate 0xeb203154 0xeb203158 $(srec_cat_le_cmd) $(CONFIG_SPL_TEXT_BASE) 4 \ + -generate 0xeb203158 0xeb203264 $(srec_cat_le_cmd) 0x0 4 \ + -generate 0xeb203264 0xeb203268 $(srec_cat_le_cmd) $$(( ( $2 + 4 ) / 4 )) 4 +else ifneq ($(CONFIG_R8A774C0)$(CONFIG_R8A77990)$(CONFIG_R8A77995),) # # The first 6 generate statements generate the R-Car Gen3 SCIF loader header. @@ -90,6 +99,7 @@ quiet_cmd_srec_cat = SRECCAT $@ -generate 0xe6301154 0xe6301158 $(srec_cat_le_cmd) $(CONFIG_SPL_TEXT_BASE) 4 \ -generate 0xe6301264 0xe6301268 $(srec_cat_le_cmd) $2 4 endif +endif spl/u-boot-spl.scif: spl/u-boot-spl.srec spl/u-boot-spl.bin $(call cmd,srec_cat,$(shell wc -c spl/u-boot-spl.bin | awk '{printf("0x%08x\n",$$1)}')) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 9a17ccb2d3d..4e26b3940d8 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -1598,7 +1598,7 @@ config SPL_OPENSBI_SCRATCH_OPTIONS config SPL_TARGET string "Addtional build targets for 'make'" default "spl/u-boot-spl.srec" if RCAR_GEN2 - default "spl/u-boot-spl.scif" if RCAR_GEN3 + default "spl/u-boot-spl.scif" if RCAR_64 default "" help On some platforms we need to have 'make' run additional build target -- cgit v1.2.3 From 45e0a55ff69fea0c986f36ab3f9462d6b11c4383 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 30 Jun 2025 20:51:10 +0200 Subject: net: sh_eth: Pass struct port_info around The struct sh_eth_dev .port member is always set to 0, therefore only single-ported SH Ethernet is ever used. Support for multiple SH Ethernet ports implemented on driver level is a remnant from before U-Boot DM existed. Pass struct sh_eth_info port_info around directly and remove the struct sh_eth_dev entirely. Handling of multiple ports should be done by U-Boot DM and multiple per-driver-instance private data. No functional change intended. Signed-off-by: Marek Vasut --- drivers/net/sh_eth.c | 136 ++++++++++++++++++++------------------------------- drivers/net/sh_eth.h | 8 --- 2 files changed, 52 insertions(+), 92 deletions(-) diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index f695a3a41d2..339a4771586 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -64,10 +64,9 @@ #define TIMEOUT_CNT 1000 -static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len) +static int sh_eth_send_common(struct sh_eth_info *port_info, void *packet, int len) { int ret = 0, timeout; - struct sh_eth_info *port_info = ð->port_info[eth->port]; if (!packet || len > 0xffff) { printf(SHETHER_NAME ": %s: Invalid argument\n", __func__); @@ -121,10 +120,8 @@ err: return ret; } -static int sh_eth_recv_start(struct sh_eth_dev *eth) +static int sh_eth_recv_start(struct sh_eth_info *port_info) { - struct sh_eth_info *port_info = ð->port_info[eth->port]; - /* Check if the rx descriptor is ready */ invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s)); if (port_info->rx_desc_cur->rd0 & RD_RACT) @@ -137,10 +134,8 @@ static int sh_eth_recv_start(struct sh_eth_dev *eth) return port_info->rx_desc_cur->rd1 & 0xffff; } -static void sh_eth_recv_finish(struct sh_eth_dev *eth) +static void sh_eth_recv_finish(struct sh_eth_info *port_info) { - struct sh_eth_info *port_info = ð->port_info[eth->port]; - invalidate_cache(ADDR_TO_P2(port_info->rx_desc_cur->rd2), MAX_BUF_SIZE); /* Make current descriptor available again */ @@ -159,9 +154,8 @@ static void sh_eth_recv_finish(struct sh_eth_dev *eth) port_info->rx_desc_cur = port_info->rx_desc_base; } -static int sh_eth_reset(struct sh_eth_dev *eth) +static int sh_eth_reset(struct sh_eth_info *port_info) { - struct sh_eth_info *port_info = ð->port_info[eth->port]; #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) int ret = 0, i; @@ -192,12 +186,11 @@ static int sh_eth_reset(struct sh_eth_dev *eth) #endif } -static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) +static int sh_eth_tx_desc_init(struct sh_eth_info *port_info) { - int i, ret = 0; u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s); - struct sh_eth_info *port_info = ð->port_info[eth->port]; struct tx_desc_s *cur_tx_desc; + int i, ret = 0; /* * Allocate rx descriptors. They must be aligned to size of struct @@ -244,11 +237,10 @@ err: return ret; } -static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) +static int sh_eth_rx_desc_init(struct sh_eth_info *port_info) { int i, ret = 0; u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s); - struct sh_eth_info *port_info = ð->port_info[eth->port]; struct rx_desc_s *cur_rx_desc; u8 *rx_buf; @@ -318,20 +310,16 @@ err: return ret; } -static void sh_eth_tx_desc_free(struct sh_eth_dev *eth) +static void sh_eth_tx_desc_free(struct sh_eth_info *port_info) { - struct sh_eth_info *port_info = ð->port_info[eth->port]; - if (port_info->tx_desc_alloc) { free(port_info->tx_desc_alloc); port_info->tx_desc_alloc = NULL; } } -static void sh_eth_rx_desc_free(struct sh_eth_dev *eth) +static void sh_eth_rx_desc_free(struct sh_eth_info *port_info) { - struct sh_eth_info *port_info = ð->port_info[eth->port]; - if (port_info->rx_desc_alloc) { free(port_info->rx_desc_alloc); port_info->rx_desc_alloc = NULL; @@ -343,21 +331,21 @@ static void sh_eth_rx_desc_free(struct sh_eth_dev *eth) } } -static int sh_eth_desc_init(struct sh_eth_dev *eth) +static int sh_eth_desc_init(struct sh_eth_info *port_info) { int ret = 0; - ret = sh_eth_tx_desc_init(eth); + ret = sh_eth_tx_desc_init(port_info); if (ret) goto err_tx_init; - ret = sh_eth_rx_desc_init(eth); + ret = sh_eth_rx_desc_init(port_info); if (ret) goto err_rx_init; return ret; err_rx_init: - sh_eth_tx_desc_free(eth); + sh_eth_tx_desc_free(port_info); err_tx_init: return ret; @@ -375,9 +363,8 @@ static void sh_eth_write_hwaddr(struct sh_eth_info *port_info, sh_eth_write(port_info, val, MALR); } -static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac) +static void sh_eth_mac_regs_config(struct sh_eth_info *port_info, unsigned char *mac) { - struct sh_eth_info *port_info = ð->port_info[eth->port]; unsigned long edmr; /* Configure e-dmac registers */ @@ -422,9 +409,8 @@ static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac) #endif } -static int sh_eth_phy_regs_config(struct sh_eth_dev *eth) +static int sh_eth_phy_regs_config(struct sh_eth_info *port_info) { - struct sh_eth_info *port_info = ð->port_info[eth->port]; struct phy_device *phy = port_info->phydev; int ret = 0; u32 val = 0; @@ -470,10 +456,8 @@ static int sh_eth_phy_regs_config(struct sh_eth_dev *eth) return ret; } -static void sh_eth_start(struct sh_eth_dev *eth) +static void sh_eth_start(struct sh_eth_info *port_info) { - struct sh_eth_info *port_info = ð->port_info[eth->port]; - /* * Enable the e-dmac receiver only. The transmitter will be enabled when * we have something to transmit @@ -481,33 +465,30 @@ static void sh_eth_start(struct sh_eth_dev *eth) sh_eth_write(port_info, EDRRR_R, EDRRR); } -static void sh_eth_stop(struct sh_eth_dev *eth) +static void sh_eth_stop(struct sh_eth_info *port_info) { - struct sh_eth_info *port_info = ð->port_info[eth->port]; - sh_eth_write(port_info, ~EDRRR_R, EDRRR); } -static int sh_eth_init_common(struct sh_eth_dev *eth, unsigned char *mac) +static int sh_eth_init_common(struct sh_eth_info *port_info, unsigned char *mac) { int ret = 0; - ret = sh_eth_reset(eth); + ret = sh_eth_reset(port_info); if (ret) return ret; - ret = sh_eth_desc_init(eth); + ret = sh_eth_desc_init(port_info); if (ret) return ret; - sh_eth_mac_regs_config(eth, mac); + sh_eth_mac_regs_config(port_info, mac); return 0; } -static int sh_eth_start_common(struct sh_eth_dev *eth) +static int sh_eth_start_common(struct sh_eth_info *port_info) { - struct sh_eth_info *port_info = ð->port_info[eth->port]; int ret; ret = phy_startup(port_info->phydev); @@ -516,17 +497,17 @@ static int sh_eth_start_common(struct sh_eth_dev *eth) return ret; } - ret = sh_eth_phy_regs_config(eth); + ret = sh_eth_phy_regs_config(port_info); if (ret) return ret; - sh_eth_start(eth); + sh_eth_start(port_info); return 0; } struct sh_ether_priv { - struct sh_eth_dev shdev; + struct sh_eth_info port_info; struct mii_dev *bus; phys_addr_t iobase; @@ -536,20 +517,19 @@ struct sh_ether_priv { static int sh_ether_send(struct udevice *dev, void *packet, int len) { struct sh_ether_priv *priv = dev_get_priv(dev); - struct sh_eth_dev *eth = &priv->shdev; + struct sh_eth_info *port_info = &priv->port_info; - return sh_eth_send_common(eth, packet, len); + return sh_eth_send_common(port_info, packet, len); } static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp) { struct sh_ether_priv *priv = dev_get_priv(dev); - struct sh_eth_dev *eth = &priv->shdev; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = &priv->port_info; uchar *packet = (uchar *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_cur->rd2); int len; - len = sh_eth_recv_start(eth); + len = sh_eth_recv_start(port_info); if (len > 0) { invalidate_cache(packet, len); *packetp = packet; @@ -567,10 +547,9 @@ static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp) static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length) { struct sh_ether_priv *priv = dev_get_priv(dev); - struct sh_eth_dev *eth = &priv->shdev; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = &priv->port_info; - sh_eth_recv_finish(eth); + sh_eth_recv_finish(port_info); /* Restart the receiver if disabled */ if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R)) @@ -582,8 +561,7 @@ static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length) static int sh_ether_write_hwaddr(struct udevice *dev) { struct sh_ether_priv *priv = dev_get_priv(dev); - struct sh_eth_dev *eth = &priv->shdev; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = &priv->port_info; struct eth_pdata *pdata = dev_get_plat(dev); sh_eth_write_hwaddr(port_info, pdata->enetaddr); @@ -595,10 +573,9 @@ static int sh_eth_phy_config(struct udevice *dev) { struct sh_ether_priv *priv = dev_get_priv(dev); struct eth_pdata *pdata = dev_get_plat(dev); - struct sh_eth_dev *eth = &priv->shdev; - int ret = 0; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = &priv->port_info; struct phy_device *phydev; + int ret = 0; phydev = phy_connect(priv->bus, -1, dev, pdata->phy_interface); if (!phydev) @@ -614,40 +591,38 @@ static int sh_ether_start(struct udevice *dev) { struct sh_ether_priv *priv = dev_get_priv(dev); struct eth_pdata *pdata = dev_get_plat(dev); - struct sh_eth_dev *eth = &priv->shdev; + struct sh_eth_info *port_info = &priv->port_info; int ret; - ret = sh_eth_init_common(eth, pdata->enetaddr); + ret = sh_eth_init_common(port_info, pdata->enetaddr); if (ret) return ret; - ret = sh_eth_start_common(eth); + ret = sh_eth_start_common(port_info); if (ret) goto err_start; return 0; err_start: - sh_eth_tx_desc_free(eth); - sh_eth_rx_desc_free(eth); + sh_eth_tx_desc_free(port_info); + sh_eth_rx_desc_free(port_info); return ret; } static void sh_ether_stop(struct udevice *dev) { struct sh_ether_priv *priv = dev_get_priv(dev); - struct sh_eth_dev *eth = &priv->shdev; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = &priv->port_info; phy_shutdown(port_info->phydev); - sh_eth_stop(&priv->shdev); + sh_eth_stop(port_info); } /******* for bb_miiphy *******/ static int sh_eth_bb_mdio_active(struct mii_dev *miidev) { - struct sh_eth_dev *eth = miidev->priv; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = miidev->priv; sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR); @@ -656,8 +631,7 @@ static int sh_eth_bb_mdio_active(struct mii_dev *miidev) static int sh_eth_bb_mdio_tristate(struct mii_dev *miidev) { - struct sh_eth_dev *eth = miidev->priv; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = miidev->priv; sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR); @@ -666,8 +640,7 @@ static int sh_eth_bb_mdio_tristate(struct mii_dev *miidev) static int sh_eth_bb_set_mdio(struct mii_dev *miidev, int v) { - struct sh_eth_dev *eth = miidev->priv; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = miidev->priv; if (v) sh_eth_write(port_info, @@ -681,8 +654,7 @@ static int sh_eth_bb_set_mdio(struct mii_dev *miidev, int v) static int sh_eth_bb_get_mdio(struct mii_dev *miidev, int *v) { - struct sh_eth_dev *eth = miidev->priv; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = miidev->priv; *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3; @@ -691,8 +663,7 @@ static int sh_eth_bb_get_mdio(struct mii_dev *miidev, int *v) static int sh_eth_bb_set_mdc(struct mii_dev *miidev, int v) { - struct sh_eth_dev *eth = miidev->priv; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = miidev->priv; if (v) sh_eth_write(port_info, @@ -738,7 +709,7 @@ static int sh_ether_probe(struct udevice *udev) { struct eth_pdata *pdata = dev_get_plat(udev); struct sh_ether_priv *priv = dev_get_priv(udev); - struct sh_eth_dev *eth = &priv->shdev; + struct sh_eth_info *port_info = &priv->port_info; struct mii_dev *mdiodev; int ret; @@ -757,7 +728,7 @@ static int sh_ether_probe(struct udevice *udev) mdiodev->read = sh_eth_bb_miiphy_read; mdiodev->write = sh_eth_bb_miiphy_write; - mdiodev->priv = eth; + mdiodev->priv = port_info; snprintf(mdiodev->name, sizeof(mdiodev->name), udev->name); ret = mdio_register(mdiodev); @@ -766,10 +737,8 @@ static int sh_ether_probe(struct udevice *udev) priv->bus = mdiodev; - eth->port = CFG_SH_ETHER_USE_PORT; - eth->port_info[eth->port].phy_addr = CFG_SH_ETHER_PHY_ADDR; - eth->port_info[eth->port].iobase = - (void __iomem *)(uintptr_t)(BASE_IO_ADDR + 0x800 * eth->port); + port_info->phy_addr = CFG_SH_ETHER_PHY_ADDR; + port_info->iobase = (void __iomem *)(uintptr_t)BASE_IO_ADDR; #if CONFIG_IS_ENABLED(CLK) ret = clk_enable(&priv->clk); @@ -777,7 +746,7 @@ static int sh_ether_probe(struct udevice *udev) goto err_mdio_register; #endif - ret = sh_eth_init_common(eth, pdata->enetaddr); + ret = sh_eth_init_common(port_info, pdata->enetaddr); if (ret) goto err_phy_config; @@ -801,8 +770,7 @@ err_mdio_register: static int sh_ether_remove(struct udevice *udev) { struct sh_ether_priv *priv = dev_get_priv(udev); - struct sh_eth_dev *eth = &priv->shdev; - struct sh_eth_info *port_info = ð->port_info[eth->port]; + struct sh_eth_info *port_info = &priv->port_info; #if CONFIG_IS_ENABLED(CLK) clk_disable(&priv->clk); diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index ecf4a697e27..6b7f8ae5154 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -33,9 +33,6 @@ #define CFG_SH_ETHER_ALIGNE_SIZE 16 #endif -/* Number of supported ports */ -#define MAX_PORT_NUM 2 - /* Buffers must be big enough to hold the largest ethernet frame. Also, rx buffers must be a multiple of 32 bytes */ #define MAX_BUF_SIZE (48 * 32) @@ -90,11 +87,6 @@ struct sh_eth_info { void __iomem *iobase; }; -struct sh_eth_dev { - int port; - struct sh_eth_info port_info[MAX_PORT_NUM]; -}; - /* from linux/drivers/net/ethernet/renesas/sh_eth.h */ enum { /* E-DMAC registers */ -- cgit v1.2.3 From fc85e55205e518fa148a36db04eec37d65e83e24 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 30 Jun 2025 20:51:11 +0200 Subject: net: sh_eth: arm: renesas: README: Drop CFG_SH_ETHER_USE_PORT The CFG_SH_ETHER_USE_PORT configuration option is a remnant from before U-Boot DM existed and SH Ethernet made full use of it, and is no longer used, remove it. Signed-off-by: Marek Vasut --- README | 3 --- drivers/net/sh_eth.c | 3 --- include/configs/alt.h | 1 - include/configs/condor.h | 1 - include/configs/gose.h | 1 - include/configs/grpeach.h | 1 - include/configs/koelsch.h | 1 - include/configs/lager.h | 1 - include/configs/porter.h | 1 - include/configs/silk.h | 1 - include/configs/stout.h | 1 - include/configs/v3hsk.h | 1 - 12 files changed, 16 deletions(-) diff --git a/README b/README index 40326ef3547..8f8f4b85ef8 100644 --- a/README +++ b/README @@ -379,9 +379,6 @@ The following options need to be configured: CONFIG_SH_ETHER Support for Renesas on-chip Ethernet controller - CFG_SH_ETHER_USE_PORT - Define the number of ports to be used - CFG_SH_ETHER_PHY_ADDR Define the ETH PHY's address diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 339a4771586..9ccba153f36 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -29,9 +29,6 @@ #include "sh_eth.h" -#ifndef CFG_SH_ETHER_USE_PORT -# error "Please define CFG_SH_ETHER_USE_PORT" -#endif #ifndef CFG_SH_ETHER_PHY_ADDR # error "Please define CFG_SH_ETHER_PHY_ADDR" #endif diff --git a/include/configs/alt.h b/include/configs/alt.h index 8f03762583e..52b8c95cd7b 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -21,7 +21,6 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* SH Ether */ -#define CFG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK diff --git a/include/configs/condor.h b/include/configs/condor.h index 50c8d173383..ecaf58e4c0f 100644 --- a/include/configs/condor.h +++ b/include/configs/condor.h @@ -14,7 +14,6 @@ /* Environment compatibility */ /* SH Ether */ -#define CFG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK diff --git a/include/configs/gose.h b/include/configs/gose.h index 7ae0726518d..323977e9b8a 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -20,7 +20,6 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512u * 1024 * 1024) /* SH Ether */ -#define CFG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index 8de4a36e931..67ad8339816 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -17,7 +17,6 @@ #define CFG_SYS_SDRAM_SIZE (10 * 1024 * 1024) /* Network interface */ -#define CFG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII #define CFG_SH_ETHER_CACHE_WRITEBACK diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index d47d70178cc..11f637d3f33 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -20,7 +20,6 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* SH Ether */ -#define CFG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK diff --git a/include/configs/lager.h b/include/configs/lager.h index 2577c7a7da6..aaf4a4a6931 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -21,7 +21,6 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* SH Ether */ -#define CFG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK diff --git a/include/configs/porter.h b/include/configs/porter.h index 2cb430be8b0..ff99c3fb817 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -22,7 +22,6 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024) /* SH Ether */ -#define CFG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK diff --git a/include/configs/silk.h b/include/configs/silk.h index 7bed32d8553..20d18aa5aa7 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -22,7 +22,6 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* SH Ether */ -#define CFG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK diff --git a/include/configs/stout.h b/include/configs/stout.h index 1278ba63f4f..454d8ca5716 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -26,7 +26,6 @@ #define CFG_SCIF_A /* SH Ether */ -#define CFG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK diff --git a/include/configs/v3hsk.h b/include/configs/v3hsk.h index 58c2e88c0b7..e16a289ac1a 100644 --- a/include/configs/v3hsk.h +++ b/include/configs/v3hsk.h @@ -15,7 +15,6 @@ /* Environment compatibility */ /* SH Ether */ -#define CFG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x0 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID #define CFG_SH_ETHER_CACHE_WRITEBACK -- cgit v1.2.3 From 16a900210956fe7c476b2355c7090c2cc078f71d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 30 Jun 2025 20:51:12 +0200 Subject: net: sh_eth: Convert cache operations to static functions Turn the current cache operation macros into static functions to improve compiler coverage checking. This does change the driver behavior slightly, the driver now expects those cache operation functions to be available on all architectures on which it is used. This should pose no problem, as the driver is only used on 32bit and 64bit ARM, which both have those operations. The CFG_SH_ETHER_ALIGNE_SIZE is converted to SH_ETHER_ALIGN_SIZE and defined as either 64 on ARM or 16 on SH. Signed-off-by: Marek Vasut --- drivers/net/sh_eth.c | 43 ++++++++++++++++++------------------------- drivers/net/sh_eth.h | 19 ++++++++----------- 2 files changed, 26 insertions(+), 36 deletions(-) diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 9ccba153f36..d372ece8e46 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -33,31 +33,24 @@ # error "Please define CFG_SH_ETHER_PHY_ADDR" #endif -#if defined(CFG_SH_ETHER_CACHE_WRITEBACK) && \ - !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) -#define flush_cache_wback(addr, len) \ - flush_dcache_range((unsigned long)addr, \ - (unsigned long)(addr + ALIGN(len, CFG_SH_ETHER_ALIGNE_SIZE))) -#else -#define flush_cache_wback(...) -#endif +static void flush_cache_wback(void *addr, unsigned long len) +{ + flush_dcache_range((unsigned long)addr, + (unsigned long)(addr + ALIGN(len, SH_ETHER_ALIGN_SIZE))); +} -#if defined(CFG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM) -#define invalidate_cache(addr, len) \ - { \ - unsigned long line_size = CFG_SH_ETHER_ALIGNE_SIZE; \ - unsigned long start, end; \ - \ - start = (unsigned long)addr; \ - end = start + len; \ - start &= ~(line_size - 1); \ - end = ((end + line_size - 1) & ~(line_size - 1)); \ - \ - invalidate_dcache_range(start, end); \ - } -#else -#define invalidate_cache(...) -#endif +static void invalidate_cache(void *addr, unsigned long len) +{ + unsigned long line_size = SH_ETHER_ALIGN_SIZE; + unsigned long start, end; + + start = (unsigned long)addr; + end = start + len; + start &= ~(line_size - 1); + end = (end + line_size - 1) & ~(line_size - 1); + + invalidate_dcache_range(start, end); +} #define TIMEOUT_CNT 1000 @@ -133,7 +126,7 @@ static int sh_eth_recv_start(struct sh_eth_info *port_info) static void sh_eth_recv_finish(struct sh_eth_info *port_info) { - invalidate_cache(ADDR_TO_P2(port_info->rx_desc_cur->rd2), MAX_BUF_SIZE); + invalidate_cache((void *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_cur->rd2), MAX_BUF_SIZE); /* Make current descriptor available again */ if (port_info->rx_desc_cur->rd0 & RD_RDLE) diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index 6b7f8ae5154..006f12a37b9 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -19,20 +19,17 @@ /* The ethernet controller needs to use physical addresses */ #define ADDR_TO_PHY(addr) ((uintptr_t)(addr) & ~0xe0000000) +#define SH_ETHER_ALIGN_SIZE 16 #elif defined(CONFIG_ARM) #ifndef inl #define inl readl #define outl writel +#define SH_ETHER_ALIGN_SIZE 64 #endif #define ADDR_TO_PHY(addr) ((uintptr_t)(addr)) #define ADDR_TO_P2(addr) (addr) #endif /* defined(CONFIG_SH) */ -/* base padding size is 16 */ -#ifndef CFG_SH_ETHER_ALIGNE_SIZE -#define CFG_SH_ETHER_ALIGNE_SIZE 16 -#endif - /* Buffers must be big enough to hold the largest ethernet frame. Also, rx buffers must be a multiple of 32 bytes */ #define MAX_BUF_SIZE (48 * 32) @@ -44,7 +41,7 @@ /* The size of the tx descriptor is determined by how much padding is used. 4, 20, or 52 bytes of padding can be used */ -#define TX_DESC_PADDING (CFG_SH_ETHER_ALIGNE_SIZE - 12) +#define TX_DESC_PADDING (SH_ETHER_ALIGN_SIZE - 12) /* Tx descriptor. We always use 3 bytes of padding */ struct tx_desc_s { @@ -59,9 +56,9 @@ struct tx_desc_s { /* The size of the rx descriptor is determined by how much padding is used. 4, 20, or 52 bytes of padding can be used */ -#define RX_DESC_PADDING (CFG_SH_ETHER_ALIGNE_SIZE - 12) +#define RX_DESC_PADDING (SH_ETHER_ALIGN_SIZE - 12) /* aligned cache line size */ -#define RX_BUF_ALIGNE_SIZE (CFG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32) +#define RX_BUF_ALIGNE_SIZE (SH_ETHER_ALIGN_SIZE > 32 ? 64 : 32) /* Rx descriptor. We always use 4 bytes of padding */ struct rx_desc_s { @@ -380,11 +377,11 @@ enum DMAC_M_BIT { #endif }; -#if CFG_SH_ETHER_ALIGNE_SIZE == 64 +#if SH_ETHER_ALIGN_SIZE == 64 # define EMDR_DESC EDMR_DL1 -#elif CFG_SH_ETHER_ALIGNE_SIZE == 32 +#elif SH_ETHER_ALIGN_SIZE == 32 # define EMDR_DESC EDMR_DL0 -#elif CFG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */ +#elif SH_ETHER_ALIGN_SIZE == 16 /* Default */ # define EMDR_DESC 0 #endif -- cgit v1.2.3 From 787dafb15a8ea2bcbeabaf68a3c87ac80b814390 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 30 Jun 2025 20:51:13 +0200 Subject: net: sh_eth: arm: renesas: README: Drop CFG_SH_ETHER_CACHE_* Drop CFG_SH_ETHER_CACHE_WRITEBACK and CFG_SH_ETHER_CACHE_INVALIDATE, which are now always enabled in the sh_eth driver, because those cache operations are always available. On architectures which do not implement cache operations yet, cache operations have to be implemented first. CFG_SH_ETHER_ALIGNE_SIZE now set as SH_ETHER_ALIGN_SIZE in sh_eth.h based on architecture and no longer configured on board level. Remove CFG_SH_ETHER_CACHE_WRITEBACK configuration option from README. Signed-off-by: Marek Vasut --- README | 3 --- include/configs/alt.h | 3 --- include/configs/condor.h | 3 --- include/configs/gose.h | 3 --- include/configs/grpeach.h | 3 --- include/configs/koelsch.h | 3 --- include/configs/lager.h | 3 --- include/configs/porter.h | 3 --- include/configs/silk.h | 3 --- include/configs/stout.h | 3 --- include/configs/v3hsk.h | 3 --- 11 files changed, 33 deletions(-) diff --git a/README b/README index 8f8f4b85ef8..7acf39540c2 100644 --- a/README +++ b/README @@ -382,9 +382,6 @@ The following options need to be configured: CFG_SH_ETHER_PHY_ADDR Define the ETH PHY's address - CFG_SH_ETHER_CACHE_WRITEBACK - If this option is set, the driver enables cache flush. - - TPM Support: CONFIG_TPM Support TPM devices. diff --git a/include/configs/alt.h b/include/configs/alt.h index 52b8c95cd7b..987fd25bb4c 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -23,9 +23,6 @@ /* SH Ether */ #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/condor.h b/include/configs/condor.h index ecaf58e4c0f..b2d66c785fc 100644 --- a/include/configs/condor.h +++ b/include/configs/condor.h @@ -16,9 +16,6 @@ /* SH Ether */ #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ /* XTAL_CLK : 33.33MHz */ diff --git a/include/configs/gose.h b/include/configs/gose.h index 323977e9b8a..acef925855a 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -22,9 +22,6 @@ /* SH Ether */ #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index 67ad8339816..9a7eef57c87 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -19,8 +19,5 @@ /* Network interface */ #define CFG_SH_ETHER_PHY_ADDR 0 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 #endif /* __GRPEACH_H */ diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index 11f637d3f33..13d2127ac13 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -22,9 +22,6 @@ /* SH Ether */ #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/lager.h b/include/configs/lager.h index aaf4a4a6931..d76f003e391 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -23,9 +23,6 @@ /* SH Ether */ #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/porter.h b/include/configs/porter.h index ff99c3fb817..eaf5d31c1d3 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -24,9 +24,6 @@ /* SH Ether */ #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/silk.h b/include/configs/silk.h index 20d18aa5aa7..4ef70281dda 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -24,9 +24,6 @@ /* SH Ether */ #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/stout.h b/include/configs/stout.h index 454d8ca5716..cb544de243e 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -28,9 +28,6 @@ /* SH Ether */ #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/v3hsk.h b/include/configs/v3hsk.h index e16a289ac1a..a8d1641b36e 100644 --- a/include/configs/v3hsk.h +++ b/include/configs/v3hsk.h @@ -17,9 +17,6 @@ /* SH Ether */ #define CFG_SH_ETHER_PHY_ADDR 0x0 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ /* XTAL_CLK : 33.33MHz */ -- cgit v1.2.3 From 397b5e9ce4896dfa20451bf3a5a41ba03208d61d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 30 Jun 2025 20:51:14 +0200 Subject: net: sh_eth: Drop phy_addr assignment Drop unused struct sh_eth_info *port_info .phy_addr member assignment. PHY address is extracted from control DT. No functional change intended. Signed-off-by: Marek Vasut --- drivers/net/sh_eth.c | 1 - drivers/net/sh_eth.h | 1 - 2 files changed, 2 deletions(-) diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index d372ece8e46..4d9cdf17b46 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -727,7 +727,6 @@ static int sh_ether_probe(struct udevice *udev) priv->bus = mdiodev; - port_info->phy_addr = CFG_SH_ETHER_PHY_ADDR; port_info->iobase = (void __iomem *)(uintptr_t)BASE_IO_ADDR; #if CONFIG_IS_ENABLED(CLK) diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index 006f12a37b9..c395e6e8fc7 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -78,7 +78,6 @@ struct sh_eth_info { u8 *rx_buf_alloc; u8 *rx_buf_base; u8 mac_addr[6]; - u8 phy_addr; struct eth_device *dev; struct phy_device *phydev; void __iomem *iobase; -- cgit v1.2.3 From e583ea549ef56f1d867ef1beb99049206973e6b6 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 30 Jun 2025 20:51:15 +0200 Subject: net: sh_eth: arm: renesas: README: Drop CFG_SH_ETHER_PHY_ADDR Drop CFG_SH_ETHER_PHY_ADDR from README and configuration files, this value is never used, PHY address is extracted from control DT instead. No functional change intended. Signed-off-by: Marek Vasut --- README | 3 --- drivers/net/sh_eth.c | 4 ---- include/configs/alt.h | 1 - include/configs/condor.h | 1 - include/configs/gose.h | 1 - include/configs/grpeach.h | 1 - include/configs/koelsch.h | 1 - include/configs/lager.h | 1 - include/configs/porter.h | 1 - include/configs/silk.h | 1 - include/configs/stout.h | 1 - include/configs/v3hsk.h | 1 - 12 files changed, 17 deletions(-) diff --git a/README b/README index 7acf39540c2..dbf66bd83ac 100644 --- a/README +++ b/README @@ -379,9 +379,6 @@ The following options need to be configured: CONFIG_SH_ETHER Support for Renesas on-chip Ethernet controller - CFG_SH_ETHER_PHY_ADDR - Define the ETH PHY's address - - TPM Support: CONFIG_TPM Support TPM devices. diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 4d9cdf17b46..1160c1d6cfa 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -29,10 +29,6 @@ #include "sh_eth.h" -#ifndef CFG_SH_ETHER_PHY_ADDR -# error "Please define CFG_SH_ETHER_PHY_ADDR" -#endif - static void flush_cache_wback(void *addr, unsigned long len) { flush_dcache_range((unsigned long)addr, diff --git a/include/configs/alt.h b/include/configs/alt.h index 987fd25bb4c..7db01cedb8b 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -21,7 +21,6 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* SH Ether */ -#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII /* Board Clock */ diff --git a/include/configs/condor.h b/include/configs/condor.h index b2d66c785fc..3be0f99ec4b 100644 --- a/include/configs/condor.h +++ b/include/configs/condor.h @@ -14,7 +14,6 @@ /* Environment compatibility */ /* SH Ether */ -#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII /* Board Clock */ diff --git a/include/configs/gose.h b/include/configs/gose.h index acef925855a..a5537ee30b2 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -20,7 +20,6 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512u * 1024 * 1024) /* SH Ether */ -#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII /* Board Clock */ diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index 9a7eef57c87..9c47fbf1c90 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -17,7 +17,6 @@ #define CFG_SYS_SDRAM_SIZE (10 * 1024 * 1024) /* Network interface */ -#define CFG_SH_ETHER_PHY_ADDR 0 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII #endif /* __GRPEACH_H */ diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index 13d2127ac13..cc6266d4d6c 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -20,7 +20,6 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* SH Ether */ -#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII /* Board Clock */ diff --git a/include/configs/lager.h b/include/configs/lager.h index d76f003e391..f59f44f1862 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -21,7 +21,6 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* SH Ether */ -#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII /* Board Clock */ diff --git a/include/configs/porter.h b/include/configs/porter.h index eaf5d31c1d3..265a0d775a3 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -22,7 +22,6 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024) /* SH Ether */ -#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII /* Board Clock */ diff --git a/include/configs/silk.h b/include/configs/silk.h index 4ef70281dda..459b9b86797 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -22,7 +22,6 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* SH Ether */ -#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII /* Board Clock */ diff --git a/include/configs/stout.h b/include/configs/stout.h index cb544de243e..d1accb90d9f 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -26,7 +26,6 @@ #define CFG_SCIF_A /* SH Ether */ -#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII /* Board Clock */ diff --git a/include/configs/v3hsk.h b/include/configs/v3hsk.h index a8d1641b36e..c5685b4c6c1 100644 --- a/include/configs/v3hsk.h +++ b/include/configs/v3hsk.h @@ -15,7 +15,6 @@ /* Environment compatibility */ /* SH Ether */ -#define CFG_SH_ETHER_PHY_ADDR 0x0 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID /* Board Clock */ -- cgit v1.2.3 From f8e0b532644c70ab4c910d6db73ea5d69b88422d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 30 Jun 2025 20:51:16 +0200 Subject: net: sh_eth: arm: renesas: README: Drop CFG_SH_ETHER_PHY_MODE Drop CFG_SH_ETHER_PHY_MODE from configuration files, this value is never used. No functional change intended. Signed-off-by: Marek Vasut --- include/configs/alt.h | 3 --- include/configs/condor.h | 3 --- include/configs/gose.h | 3 --- include/configs/grpeach.h | 3 --- include/configs/koelsch.h | 3 --- include/configs/lager.h | 3 --- include/configs/porter.h | 3 --- include/configs/silk.h | 3 --- include/configs/stout.h | 3 --- include/configs/v3hsk.h | 3 --- 10 files changed, 30 deletions(-) diff --git a/include/configs/alt.h b/include/configs/alt.h index 7db01cedb8b..dfce0b3f4c8 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -20,9 +20,6 @@ #define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) -/* SH Ether */ -#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII - /* Board Clock */ #define CFG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/condor.h b/include/configs/condor.h index 3be0f99ec4b..0fb790f2413 100644 --- a/include/configs/condor.h +++ b/include/configs/condor.h @@ -13,9 +13,6 @@ /* Environment compatibility */ -/* SH Ether */ -#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII - /* Board Clock */ /* XTAL_CLK : 33.33MHz */ diff --git a/include/configs/gose.h b/include/configs/gose.h index a5537ee30b2..abd13df964d 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -19,9 +19,6 @@ #define RCAR_GEN2_SDRAM_SIZE (1048u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512u * 1024 * 1024) -/* SH Ether */ -#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII - /* Board Clock */ #define CFG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index 9c47fbf1c90..1961b4416dd 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -16,7 +16,4 @@ #define CFG_SYS_SDRAM_BASE 0x20000000 #define CFG_SYS_SDRAM_SIZE (10 * 1024 * 1024) -/* Network interface */ -#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII - #endif /* __GRPEACH_H */ diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index cc6266d4d6c..16c9e09a17f 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -19,9 +19,6 @@ #define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) -/* SH Ether */ -#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII - /* Board Clock */ #define CFG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/lager.h b/include/configs/lager.h index f59f44f1862..fbdc125d67b 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -20,9 +20,6 @@ #define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) -/* SH Ether */ -#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII - /* Board Clock */ #define CFG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/porter.h b/include/configs/porter.h index 265a0d775a3..c74ae3a42d9 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -21,9 +21,6 @@ #define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024) -/* SH Ether */ -#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII - /* Board Clock */ #define CFG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/silk.h b/include/configs/silk.h index 459b9b86797..bb59e94dc47 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -21,9 +21,6 @@ #define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) -/* SH Ether */ -#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII - /* Board Clock */ #define CFG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/stout.h b/include/configs/stout.h index d1accb90d9f..dbb5c63172d 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -25,9 +25,6 @@ /* SCIF */ #define CFG_SCIF_A -/* SH Ether */ -#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII - /* Board Clock */ #define CFG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/v3hsk.h b/include/configs/v3hsk.h index c5685b4c6c1..83e5998e7ae 100644 --- a/include/configs/v3hsk.h +++ b/include/configs/v3hsk.h @@ -14,9 +14,6 @@ /* Environment compatibility */ -/* SH Ether */ -#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID - /* Board Clock */ /* XTAL_CLK : 33.33MHz */ -- cgit v1.2.3 From 1fc646fda1ca1e4ce8479b45f06fa7d6f43314cc Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 30 Jun 2025 20:51:17 +0200 Subject: arm: renesas: configs: Drop deprecated comments Remove various deprecated code comments, no functional change. Signed-off-by: Marek Vasut --- include/configs/alt.h | 2 -- include/configs/blanche.h | 4 ---- include/configs/condor.h | 5 ----- include/configs/ebisu.h | 2 -- include/configs/falcon.h | 3 --- include/configs/gose.h | 2 -- include/configs/grpeach.h | 4 ---- include/configs/koelsch.h | 4 ---- include/configs/lager.h | 4 ---- include/configs/porter.h | 4 ---- include/configs/silk.h | 4 ---- include/configs/stout.h | 4 ---- include/configs/v3hsk.h | 5 ----- 13 files changed, 47 deletions(-) diff --git a/include/configs/alt.h b/include/configs/alt.h index dfce0b3f4c8..4c5d2de2bdf 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -20,8 +20,6 @@ #define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) -/* Board Clock */ - #define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ "usb_pgood_delay=2000\0" diff --git a/include/configs/blanche.h b/include/configs/blanche.h index d4e0f677e67..46521aa16bf 100644 --- a/include/configs/blanche.h +++ b/include/configs/blanche.h @@ -29,8 +29,4 @@ #define CFG_SYS_FLASH_BANKS_SIZES { (CFG_SYS_FLASH_SIZE) } #endif -/* Board Clock */ - -/* ENV setting */ - #endif /* __BLANCHE_H */ diff --git a/include/configs/condor.h b/include/configs/condor.h index 0fb790f2413..b340800cc11 100644 --- a/include/configs/condor.h +++ b/include/configs/condor.h @@ -11,9 +11,4 @@ #include "rcar-gen3-common.h" -/* Environment compatibility */ - -/* Board Clock */ -/* XTAL_CLK : 33.33MHz */ - #endif /* __CONDOR_H */ diff --git a/include/configs/ebisu.h b/include/configs/ebisu.h index ad5944230a6..707e7c28d55 100644 --- a/include/configs/ebisu.h +++ b/include/configs/ebisu.h @@ -9,8 +9,6 @@ #ifndef __EBISU_H #define __EBISU_H -#undef DEBUG - #include "rcar-gen3-common.h" /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/falcon.h b/include/configs/falcon.h index 0b62ff9fbe1..e1cace73550 100644 --- a/include/configs/falcon.h +++ b/include/configs/falcon.h @@ -11,7 +11,4 @@ #include "rcar-gen4-common.h" -/* Board Clock */ -/* XTAL_CLK : 16.66MHz */ - #endif /* __FALCON_H */ diff --git a/include/configs/gose.h b/include/configs/gose.h index abd13df964d..4a5954af76f 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -19,8 +19,6 @@ #define RCAR_GEN2_SDRAM_SIZE (1048u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512u * 1024 * 1024) -/* Board Clock */ - #define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index 1961b4416dd..e4564b67a79 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -8,10 +8,6 @@ #ifndef __GRPEACH_H #define __GRPEACH_H -/* Board Clock , P1 clock frequency (XTAL=13.33MHz) */ - -/* Miscellaneous */ - /* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */ #define CFG_SYS_SDRAM_BASE 0x20000000 #define CFG_SYS_SDRAM_SIZE (10 * 1024 * 1024) diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index 16c9e09a17f..c2713b77e0a 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -19,11 +19,7 @@ #define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) -/* Board Clock */ - #define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" -/* SPL support */ - #endif /* __KOELSCH_H */ diff --git a/include/configs/lager.h b/include/configs/lager.h index fbdc125d67b..13f327fabf2 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -20,11 +20,7 @@ #define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) -/* Board Clock */ - #define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" -/* SPL support */ - #endif /* __LAGER_H */ diff --git a/include/configs/porter.h b/include/configs/porter.h index c74ae3a42d9..4612845db19 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -21,11 +21,7 @@ #define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024) -/* Board Clock */ - #define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" -/* SPL support */ - #endif /* __PORTER_H */ diff --git a/include/configs/silk.h b/include/configs/silk.h index bb59e94dc47..09ef2a848bd 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -21,11 +21,7 @@ #define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) -/* Board Clock */ - #define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" -/* SPL support */ - #endif /* __SILK_H */ diff --git a/include/configs/stout.h b/include/configs/stout.h index dbb5c63172d..f98ebb324f3 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -25,11 +25,7 @@ /* SCIF */ #define CFG_SCIF_A -/* Board Clock */ - #define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" -/* SPL support */ - #endif /* __STOUT_H */ diff --git a/include/configs/v3hsk.h b/include/configs/v3hsk.h index 83e5998e7ae..3298e627e53 100644 --- a/include/configs/v3hsk.h +++ b/include/configs/v3hsk.h @@ -12,9 +12,4 @@ #include "rcar-gen3-common.h" -/* Environment compatibility */ - -/* Board Clock */ -/* XTAL_CLK : 33.33MHz */ - #endif /* __V3HSK_H */ -- cgit v1.2.3 From 48ec1fd4f4d769a796b0b3430f2e5f5a87e14c54 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 8 Jun 2025 23:01:04 +0200 Subject: arm64: dts: renesas: Clean up sysinfo EEPROM DT description on R-Car Gen3 Most of the sysinfo EEPROM node eeprom@50 is now part of the core DTs, remove duplicate DT properties from *-u-boot.dtsi . Adjust the phandle reference to i2c-eeprom in sysinfo node using <&{i2c_*/eeprom@50}> to avoid need for DT label. No functional change. Signed-off-by: Marek Vasut --- arch/arm/dts/r8a77951-salvator-x-u-boot.dtsi | 5 ++--- arch/arm/dts/r8a77951-ulcb-u-boot.dtsi | 8 ++------ arch/arm/dts/r8a77960-salvator-x-u-boot.dtsi | 5 ++--- arch/arm/dts/r8a77960-ulcb-u-boot.dtsi | 8 ++------ arch/arm/dts/r8a77965-salvator-x-u-boot.dtsi | 5 ++--- arch/arm/dts/r8a77965-ulcb-u-boot.dtsi | 8 ++------ arch/arm/dts/r8a77980-condor-u-boot.dtsi | 7 ++----- arch/arm/dts/r8a77990-ebisu-u-boot.dtsi | 11 ++--------- arch/arm/dts/r8a77995-draak-u-boot.dtsi | 7 ++----- 9 files changed, 18 insertions(+), 46 deletions(-) diff --git a/arch/arm/dts/r8a77951-salvator-x-u-boot.dtsi b/arch/arm/dts/r8a77951-salvator-x-u-boot.dtsi index 744f4aaaad9..d88e839a890 100644 --- a/arch/arm/dts/r8a77951-salvator-x-u-boot.dtsi +++ b/arch/arm/dts/r8a77951-salvator-x-u-boot.dtsi @@ -10,7 +10,7 @@ / { sysinfo { compatible = "renesas,rcar-sysinfo"; - i2c-eeprom = <&sysinfo_eeprom>; + i2c-eeprom = <&{i2c_dvfs/eeprom@50}>; bootph-all; }; }; @@ -18,9 +18,8 @@ &i2c_dvfs { bootph-all; - sysinfo_eeprom: eeprom@50 { + eeprom@50 { bootph-all; - status = "okay"; }; }; diff --git a/arch/arm/dts/r8a77951-ulcb-u-boot.dtsi b/arch/arm/dts/r8a77951-ulcb-u-boot.dtsi index 305c4861520..8269d967af9 100644 --- a/arch/arm/dts/r8a77951-ulcb-u-boot.dtsi +++ b/arch/arm/dts/r8a77951-ulcb-u-boot.dtsi @@ -19,7 +19,7 @@ sysinfo { compatible = "renesas,rcar-sysinfo"; - i2c-eeprom = <&sysinfo_eeprom>; + i2c-eeprom = <&{i2c_dvfs/eeprom@50}>; bootph-all; }; }; @@ -27,12 +27,8 @@ &i2c_dvfs { bootph-all; - sysinfo_eeprom: eeprom@50 { - compatible = "rohm,br24t01", "atmel,24c01"; - reg = <0x50>; - pagesize = <8>; + eeprom@50 { bootph-all; - status = "okay"; }; }; diff --git a/arch/arm/dts/r8a77960-salvator-x-u-boot.dtsi b/arch/arm/dts/r8a77960-salvator-x-u-boot.dtsi index 84a28bf885c..0a1602cdd23 100644 --- a/arch/arm/dts/r8a77960-salvator-x-u-boot.dtsi +++ b/arch/arm/dts/r8a77960-salvator-x-u-boot.dtsi @@ -10,7 +10,7 @@ / { sysinfo { compatible = "renesas,rcar-sysinfo"; - i2c-eeprom = <&sysinfo_eeprom>; + i2c-eeprom = <&{i2c_dvfs/eeprom@50}>; bootph-all; }; }; @@ -18,9 +18,8 @@ &i2c_dvfs { bootph-all; - sysinfo_eeprom: eeprom@50 { + eeprom@50 { bootph-all; - status = "okay"; }; }; diff --git a/arch/arm/dts/r8a77960-ulcb-u-boot.dtsi b/arch/arm/dts/r8a77960-ulcb-u-boot.dtsi index 6372f953956..d2a0406be17 100644 --- a/arch/arm/dts/r8a77960-ulcb-u-boot.dtsi +++ b/arch/arm/dts/r8a77960-ulcb-u-boot.dtsi @@ -19,7 +19,7 @@ sysinfo { compatible = "renesas,rcar-sysinfo"; - i2c-eeprom = <&sysinfo_eeprom>; + i2c-eeprom = <&{i2c_dvfs/eeprom@50}>; bootph-all; }; }; @@ -27,12 +27,8 @@ &i2c_dvfs { bootph-all; - sysinfo_eeprom: eeprom@50 { - compatible = "rohm,br24t01", "atmel,24c01"; - reg = <0x50>; - pagesize = <8>; + eeprom@50 { bootph-all; - status = "okay"; }; }; diff --git a/arch/arm/dts/r8a77965-salvator-x-u-boot.dtsi b/arch/arm/dts/r8a77965-salvator-x-u-boot.dtsi index d9a28fe9bab..518466aca35 100644 --- a/arch/arm/dts/r8a77965-salvator-x-u-boot.dtsi +++ b/arch/arm/dts/r8a77965-salvator-x-u-boot.dtsi @@ -10,7 +10,7 @@ / { sysinfo { compatible = "renesas,rcar-sysinfo"; - i2c-eeprom = <&sysinfo_eeprom>; + i2c-eeprom = <&{i2c_dvfs/eeprom@50}>; bootph-all; }; }; @@ -18,9 +18,8 @@ &i2c_dvfs { bootph-all; - sysinfo_eeprom: eeprom@50 { + eeprom@50 { bootph-all; - status = "okay"; }; }; diff --git a/arch/arm/dts/r8a77965-ulcb-u-boot.dtsi b/arch/arm/dts/r8a77965-ulcb-u-boot.dtsi index aa5de3d0465..3905bf4e4f7 100644 --- a/arch/arm/dts/r8a77965-ulcb-u-boot.dtsi +++ b/arch/arm/dts/r8a77965-ulcb-u-boot.dtsi @@ -19,7 +19,7 @@ sysinfo { compatible = "renesas,rcar-sysinfo"; - i2c-eeprom = <&sysinfo_eeprom>; + i2c-eeprom = <&{i2c_dvfs/eeprom@50}>; bootph-all; }; }; @@ -27,12 +27,8 @@ &i2c_dvfs { bootph-all; - sysinfo_eeprom: eeprom@50 { - compatible = "rohm,br24t01", "atmel,24c01"; - reg = <0x50>; - pagesize = <8>; + eeprom@50 { bootph-all; - status = "okay"; }; }; diff --git a/arch/arm/dts/r8a77980-condor-u-boot.dtsi b/arch/arm/dts/r8a77980-condor-u-boot.dtsi index 34a735ae5b2..382bfe8cacd 100644 --- a/arch/arm/dts/r8a77980-condor-u-boot.dtsi +++ b/arch/arm/dts/r8a77980-condor-u-boot.dtsi @@ -14,7 +14,7 @@ sysinfo { compatible = "renesas,rcar-sysinfo"; - i2c-eeprom = <&sysinfo_eeprom>; + i2c-eeprom = <&{i2c0/eeprom@50}>; bootph-all; }; }; @@ -22,10 +22,7 @@ &i2c0 { bootph-all; - sysinfo_eeprom: eeprom@50 { - compatible = "rohm,br24t01", "atmel,24c01"; - reg = <0x50>; - pagesize = <8>; + eeprom@50 { bootph-all; }; }; diff --git a/arch/arm/dts/r8a77990-ebisu-u-boot.dtsi b/arch/arm/dts/r8a77990-ebisu-u-boot.dtsi index b6b7b8f3609..a52c5de4ddf 100644 --- a/arch/arm/dts/r8a77990-ebisu-u-boot.dtsi +++ b/arch/arm/dts/r8a77990-ebisu-u-boot.dtsi @@ -10,23 +10,16 @@ / { sysinfo { compatible = "renesas,rcar-sysinfo"; - i2c-eeprom = <&sysinfo_eeprom>; + i2c-eeprom = <&{i2c_dvfs/eeprom@50}>; bootph-all; }; }; &i2c_dvfs { - compatible = "renesas,iic-r8a77990", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; bootph-all; - sysinfo_eeprom: eeprom@50 { - compatible = "rohm,br24t01", "atmel,24c01"; - reg = <0x50>; - pagesize = <8>; + eeprom@50 { bootph-all; - status = "okay"; }; }; diff --git a/arch/arm/dts/r8a77995-draak-u-boot.dtsi b/arch/arm/dts/r8a77995-draak-u-boot.dtsi index 1922c40a438..19d19542efd 100644 --- a/arch/arm/dts/r8a77995-draak-u-boot.dtsi +++ b/arch/arm/dts/r8a77995-draak-u-boot.dtsi @@ -10,7 +10,7 @@ / { sysinfo { compatible = "renesas,rcar-sysinfo"; - i2c-eeprom = <&sysinfo_eeprom>; + i2c-eeprom = <&{i2c0/eeprom@50}>; bootph-all; }; }; @@ -18,10 +18,7 @@ &i2c0 { bootph-all; - sysinfo_eeprom: eeprom@50 { - compatible = "rohm,br24t01", "atmel,24c01"; - reg = <0x50>; - pagesize = <8>; + eeprom@50 { bootph-all; }; }; -- cgit v1.2.3 From 583b49a0ce94dca20efc72ccf6e81e61b8f9e573 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 17 Jun 2025 00:45:02 +0200 Subject: binman: Add renesas_rcar4_sa0 etype Add new etype which generates the Renesas R-Car Gen4 SA0 header. This header is placed at the beginning of SPI NOR and describes where should data from SPI NOR offset 0x40000 be loaded to, and how much data should be loaded there. In case of U-Boot, this is used to load SPL and possibly other payload(s) into RT-VRAM. Signed-off-by: Marek Vasut --- .gitignore | 1 + tools/binman/etype/renesas_rcar4_sa0.py | 46 ++++++++++++++++++++++++ tools/binman/ftest.py | 11 ++++++ tools/binman/test/348_renesas_rcar4_sa0.dts | 15 ++++++++ tools/binman/test/349_renesas_rcar4_sa0_size.dts | 20 +++++++++++ 5 files changed, 93 insertions(+) create mode 100644 tools/binman/etype/renesas_rcar4_sa0.py create mode 100644 tools/binman/test/348_renesas_rcar4_sa0.dts create mode 100644 tools/binman/test/349_renesas_rcar4_sa0_size.dts diff --git a/.gitignore b/.gitignore index 272257a77bb..bb03833b5f2 100644 --- a/.gitignore +++ b/.gitignore @@ -75,6 +75,7 @@ fit-dtb.blob* /keep-syms-lto.* /*imx8mimage* /*imx8mcst* +/*rcar4-sa0* /drivers/video/u_boot_logo.S /test/overlay/test-fdt-overlay.dtbo.S /test/overlay/test-fdt-overlay-stacked.dtbo.S diff --git a/tools/binman/etype/renesas_rcar4_sa0.py b/tools/binman/etype/renesas_rcar4_sa0.py new file mode 100644 index 00000000000..3a7c0988fdc --- /dev/null +++ b/tools/binman/etype/renesas_rcar4_sa0.py @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright 2025 Marek Vasut +# +# Entry-type module for generating the Renesas R-Car Gen4 SA0 header. +# + +import os +import struct + +from binman.etype.section import Entry_section +from dtoc import fdt_util +from u_boot_pylib import tools + +RCAR_GEN4_SF_HEADER_SIZE = 0x40000 +RCAR_GEN4_SF_MAX_LOAD_SIZE = 0xec000 + +class Entry_renesas_rcar4_sa0(Entry_section): + """Renesas R-Car Gen4 SA0 generator""" + + def __init__(self, section, etype, node): + super().__init__(section, etype, node) + self.required_props = ['renesas,loader-address'] + + def ReadNode(self): + self.loader_address = fdt_util.GetInt(self._node, 'renesas,loader-address') + super().ReadNode() + + def BuildSectionData(self, required): + data = super().BuildSectionData(required)[RCAR_GEN4_SF_HEADER_SIZE:] + + # Offset 0x0000 / Value 0x00000000 + header = struct.pack(' RCAR_GEN4_SF_MAX_LOAD_SIZE: + self.Raise(f'SRAM data longer than {RCAR_GEN4_SF_MAX_LOAD_SIZE} Bytes') + + return header + data diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py index 8225216fbec..a90db3c9351 100644 --- a/tools/binman/ftest.py +++ b/tools/binman/ftest.py @@ -5586,6 +5586,17 @@ fdt fdtmap Extract the devicetree blob from the fdtmap data = self._DoReadFile('347_bl1.dts') self.assertEqual(ATF_BL1_DATA, data[:len(ATF_BL1_DATA)]) + def testRenesasRCarGen4SA0Image(self): + """Test that binman can produce an Renesas R-Car Gen4 SA0 image""" + self._DoTestFile('348_renesas_rcar4_sa0.dts') + + def testRenesasRCarGen4SA0ImageSize(self): + """Test that binman can not produce large Renesas R-Car Gen4 SA0 image""" + with self.assertRaises(ValueError) as exc: + self._DoTestFile('349_renesas_rcar4_sa0_size.dts') + self.assertIn("Node '/binman/renesas-rcar4-sa0': SRAM data longer than 966656 Bytes", + str(exc.exception)) + def testFitFdtOper(self): """Check handling of a specified FIT operation""" entry_args = { diff --git a/tools/binman/test/348_renesas_rcar4_sa0.dts b/tools/binman/test/348_renesas_rcar4_sa0.dts new file mode 100644 index 00000000000..4a8717520f2 --- /dev/null +++ b/tools/binman/test/348_renesas_rcar4_sa0.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + renesas-rcar4-sa0 { + filename = "sa0.bin"; + renesas,loader-address = <0x10>; + }; + }; +}; diff --git a/tools/binman/test/349_renesas_rcar4_sa0_size.dts b/tools/binman/test/349_renesas_rcar4_sa0_size.dts new file mode 100644 index 00000000000..eaf4507260b --- /dev/null +++ b/tools/binman/test/349_renesas_rcar4_sa0_size.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + renesas-rcar4-sa0 { + filename = "sa0.bin"; + renesas,loader-address = <0x10>; + + fill { /* Oversize fill to cover size check */ + size = <0x140000>; + fill-byte = [ff]; + }; + }; + }; +}; -- cgit v1.2.3 From 64a2c3731f32e7b1ad360155dab3b0631ca75319 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 17 Jun 2025 00:45:03 +0200 Subject: arm64: renesas: Switch R-Car V4H to renesas_rcar4_sa0 binman etype Replace current ad-hoc generation of SA0 header with renesas_rcar4_sa0 binman etype on Renesas R-Car V4H. The new binman etype generates header which is almost identical to the current ad-hoc SA0 header, with one difference, the load length matches the actual payload size, which slightly improves boot time. Signed-off-by: Marek Vasut --- arch/arm/dts/r8a779g0-u-boot.dtsi | 78 ++++++++------------------------------- 1 file changed, 15 insertions(+), 63 deletions(-) diff --git a/arch/arm/dts/r8a779g0-u-boot.dtsi b/arch/arm/dts/r8a779g0-u-boot.dtsi index 5aa61314834..bd6a3d0713f 100644 --- a/arch/arm/dts/r8a779g0-u-boot.dtsi +++ b/arch/arm/dts/r8a779g0-u-boot.dtsi @@ -7,73 +7,25 @@ / { binman: binman { - multiple-images; - section { filename = "flash.bin"; pad-byte = <0xff>; - /* Offset 0x0000 set to 0x0000_0000 */ - fill@0 { - offset = <0x0>; - size = <0x4>; - fill-byte = [00]; - }; - - /* Offset 0x300c set to 0x0000_0000 */ - fill@300c { - offset = <0x300c>; - size = <0x4>; - fill-byte = [00]; - }; - - /* Offset 0x3154 set to 0xeb21_0000 */ - fill@3154 { - offset = <0x3154>; - size = <0x2>; - fill-byte = [00]; - }; - - fill@3156 { - offset = <0x3156>; - size = <0x1>; - fill-byte = [21]; - }; - - fill@3157 { - offset = <0x3157>; - size = <0x1>; - fill-byte = [eb]; - }; - - /* Offset 0x3264 set to 0x0003_b000 */ - fill@3264 { - offset = <0x3264>; - size = <0x1>; - fill-byte = [00]; - }; - - fill@3265 { - offset = <0x3265>; - size = <0x1>; - fill-byte = [b0]; - }; - - fill@3266 { - offset = <0x3266>; - size = <0x1>; - fill-byte = [03]; - }; - - fill@3267 { - offset = <0x3267>; - size = <0x1>; - fill-byte = [00]; - }; - - u-boot-spl { - offset = <0x40000>; - align-end = <4>; + renesas-rcar4-sa0 { + filename = "sa0.bin"; + pad-byte = <0xff>; + renesas,loader-address = ; + + /* + * This section starts after 0x40000 Bytes long + * header added by the renesas-rcar4-sa0 binman + * etype. That means u-boot-spl {} below starts + * at offset 0x40000 in flash.bin . + */ + u-boot-spl { + offset = <0x40000>; + align-end = <4>; + }; }; u-boot { -- cgit v1.2.3 From 74fc581374174c7d9622b0373dd497a2acba9087 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 7 Jul 2025 10:39:31 +0200 Subject: ARM: renesas: Split common RZ/A1 and GR-PEACH defconfigs Split the RZ/A1 GR-PEACH defconfig into board-specific defconfig and common RZ/A1 SoC defconfig. This is a preparatory patch for new RZ/A1 boards, no functional change. Signed-off-by: Marek Vasut --- configs/grpeach_defconfig | 71 +++++++-------------------------------------- configs/renesas_rza1.config | 55 +++++++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+), 61 deletions(-) create mode 100644 configs/renesas_rza1.config diff --git a/configs/grpeach_defconfig b/configs/grpeach_defconfig index 0f141b6f0a2..110af10860b 100644 --- a/configs/grpeach_defconfig +++ b/configs/grpeach_defconfig @@ -1,69 +1,18 @@ +#include + CONFIG_ARM=y -CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_RENESAS=y CONFIG_TEXT_BASE=0x18000000 -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_SYS_MALLOC_F_LEN=0x400 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20900000 -CONFIG_ENV_SIZE=0x10000 -CONFIG_ENV_OFFSET=0x80000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="renesas/r7s72100-gr-peach" -CONFIG_RZA1=y -CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_SYS_MONITOR_LEN=524288 -CONFIG_SYS_LOAD_ADDR=0x20400000 -CONFIG_SYS_CLK_FREQ=66666666 -# CONFIG_EFI_LOADER is not set -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="ignore_loglevel" -CONFIG_SYS_CBSIZE=256 -CONFIG_SYS_PBSIZE=256 -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_BOARD_EARLY_INIT_F is not set -CONFIG_HUSH_PARSER=y -# CONFIG_CMD_ELF is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_USB=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_MAC_PARTITION=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y +CONFIG_TARGET_GRPEACH=y + +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_DM_SPI_FLASH=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_ENV_SPI_MAX_HZ=50000000 +CONFIG_ENV_OFFSET=0x80000 CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_RZA1_GPIO=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -# CONFIG_MMC is not set +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_SPI_MAX_HZ=50000000 CONFIG_MTD=y -CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_BITBANGMII=y -CONFIG_PHY_SMSC=y -CONFIG_DM_ETH_PHY=y -CONFIG_SH_ETHER=y -CONFIG_PINCTRL=y -CONFIG_DM_REGULATOR=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_SCIF_CONSOLE=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_RENESAS_RPC_SPI=y -CONFIG_TIMER=y -CONFIG_RENESAS_OSTM_TIMER=y -CONFIG_USB=y -CONFIG_USB_R8A66597_HCD=y -CONFIG_USB_STORAGE=y diff --git a/configs/renesas_rza1.config b/configs/renesas_rza1.config new file mode 100644 index 00000000000..10d817f03a7 --- /dev/null +++ b/configs/renesas_rza1.config @@ -0,0 +1,55 @@ +CONFIG_ARCH_CPU_INIT=y +CONFIG_SYS_MALLOC_LEN=0x100000 +CONFIG_SYS_MALLOC_F_LEN=0x400 +# CONFIG_BOARD_EARLY_INIT_F is not set +# CONFIG_CMD_ELF is not set +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_EFI_LOADER is not set +# CONFIG_MMC is not set +CONFIG_BITBANGMII=y +CONFIG_BOOTARGS="ignore_loglevel" +CONFIG_BOOTDELAY=3 +CONFIG_CMD_CACHE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_USB=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20900000 +CONFIG_DM_ETH_PHY=y +CONFIG_DM_GPIO=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_SPI=y +CONFIG_ENV_OVERWRITE=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_HUSH_PARSER=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MAC_PARTITION=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_OF_CONTROL=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_PHY_SMSC=y +CONFIG_PINCTRL=y +CONFIG_RENESAS_OSTM_TIMER=y +CONFIG_RENESAS_RPC_SPI=y +CONFIG_RZA1=y +CONFIG_RZA1_GPIO=y +CONFIG_SCIF_CONSOLE=y +CONFIG_SH_ETHER=y +CONFIG_SPI=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_CLK_FREQ=66666666 +CONFIG_SYS_LOAD_ADDR=0x20400000 +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_SYS_PBSIZE=256 +CONFIG_TIMER=y +CONFIG_USB=y +CONFIG_USB_R8A66597_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USE_BOOTARGS=y -- cgit v1.2.3 From 6e20aa243d0b373cfd30e5c47c357d132bf795e2 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 2 Jul 2025 19:13:46 +0200 Subject: ARM: renesas: Put common r7s72100 code in board/renesas/common Break out SoC specific code from the GR-Peach board and put it into the board/renesas/common directory so it can be easily shared between the GR-Peach and Genmai boards. Signed-off-by: Magnus Damm --- board/renesas/common/Makefile | 8 +++ board/renesas/common/rza1-common.c | 27 ++++++++ board/renesas/common/rza1-lowlevel_init.S | 106 ++++++++++++++++++++++++++++++ board/renesas/grpeach/Makefile | 1 - board/renesas/grpeach/grpeach.c | 22 ------- board/renesas/grpeach/lowlevel_init.S | 106 ------------------------------ 6 files changed, 141 insertions(+), 129 deletions(-) create mode 100644 board/renesas/common/rza1-common.c create mode 100644 board/renesas/common/rza1-lowlevel_init.S delete mode 100644 board/renesas/grpeach/lowlevel_init.S diff --git a/board/renesas/common/Makefile b/board/renesas/common/Makefile index 5e51b691178..1849c995aee 100644 --- a/board/renesas/common/Makefile +++ b/board/renesas/common/Makefile @@ -5,6 +5,7 @@ # # R-Car SoCs +ifndef CONFIG_RZA1 ifndef CONFIG_RZG2L # 32 bit SoCs @@ -45,3 +46,10 @@ endif endif endif +endif + +# RZ/A1 SoCs +ifdef CONFIG_RZA1 +obj-y += rza1-common.o +obj-y += rza1-lowlevel_init.o +endif diff --git a/board/renesas/common/rza1-common.c b/board/renesas/common/rza1-common.c new file mode 100644 index 00000000000..5027319a58a --- /dev/null +++ b/board/renesas/common/rza1-common.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Renesas Electronics + * Copyright (C) Chris Brandt + */ + +#include +#include + +#define RZA1_WDT_BASE 0xfcfe0000 +#define WTCSR 0x00 +#define WTCNT 0x02 +#define WRCSR 0x04 + +void __weak reset_cpu(void) +{ + /* Dummy read (must read WRCSR:WOVF at least once before clearing) */ + readb(RZA1_WDT_BASE + WRCSR); + + writew(0xa500, RZA1_WDT_BASE + WRCSR); + writew(0x5a5f, RZA1_WDT_BASE + WRCSR); + writew(0x5a00, RZA1_WDT_BASE + WTCNT); + writew(0xa578, RZA1_WDT_BASE + WTCSR); + + for (;;) + asm volatile("wfi"); +} diff --git a/board/renesas/common/rza1-lowlevel_init.S b/board/renesas/common/rza1-lowlevel_init.S new file mode 100644 index 00000000000..b83c4e86867 --- /dev/null +++ b/board/renesas/common/rza1-lowlevel_init.S @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Renesas Electronics + * Copyright (C) 2017 Chris Brandt + */ +#include +#include + +/* Watchdog Registers */ +#define RZA1_WDT_BASE 0xFCFE0000 +#define WTCSR (RZA1_WDT_BASE + 0x00) /* Watchdog Timer Control Register */ +#define WTCNT (RZA1_WDT_BASE + 0x02) /* Watchdog Timer Counter Register */ +#define WRCSR (RZA1_WDT_BASE + 0x04) /* Watchdog Reset Control Register */ + +/* Standby controller registers (chapter 55) */ +#define RZA1_STBCR_BASE 0xFCFE0020 +#define STBCR1 (RZA1_STBCR_BASE + 0x00) +#define STBCR2 (RZA1_STBCR_BASE + 0x04) +#define STBCR3 (RZA1_STBCR_BASE + 0x400) +#define STBCR4 (RZA1_STBCR_BASE + 0x404) +#define STBCR5 (RZA1_STBCR_BASE + 0x408) +#define STBCR6 (RZA1_STBCR_BASE + 0x40c) +#define STBCR7 (RZA1_STBCR_BASE + 0x410) +#define STBCR8 (RZA1_STBCR_BASE + 0x414) +#define STBCR9 (RZA1_STBCR_BASE + 0x418) +#define STBCR10 (RZA1_STBCR_BASE + 0x41c) +#define STBCR11 (RZA1_STBCR_BASE + 0x420) +#define STBCR12 (RZA1_STBCR_BASE + 0x424) +#define STBCR13 (RZA1_STBCR_BASE + 0x450) + +/* Clock Registers */ +#define RZA1_FRQCR_BASE 0xFCFE0010 +#define FRQCR (RZA1_FRQCR_BASE + 0x00) +#define FRQCR2 (RZA1_FRQCR_BASE + 0x04) + +#define SYSCR1 0xFCFE0400 /* System control register 1 */ +#define SYSCR2 0xFCFE0404 /* System control register 2 */ +#define SYSCR3 0xFCFE0408 /* System control register 3 */ + +/* Disable WDT */ +#define WTCSR_D 0xA518 +#define WTCNT_D 0x5A00 + +/* Enable all peripheral clocks */ +#define STBCR3_D 0x00000000 +#define STBCR4_D 0x00000000 +#define STBCR5_D 0x00000000 +#define STBCR6_D 0x00000000 +#define STBCR7_D 0x00000024 +#define STBCR8_D 0x00000005 +#define STBCR9_D 0x00000000 +#define STBCR10_D 0x00000000 +#define STBCR11_D 0x000000c0 +#define STBCR12_D 0x000000f0 + +/* + * Set all system clocks to full speed. + * On reset, the CPU will be running at 1/2 speed. + * In the Hardware Manual, see Table 6.3 Settable Frequency Ranges + */ +#define FRQCR_D 0x0035 +#define FRQCR2_D 0x0001 + + .global lowlevel_init + + .text + .align 2 + +lowlevel_init: + /* PL310 init */ + write32 0x3fffff80, 0x00000001 + + /* Disable WDT */ + write16 WTCSR, WTCSR_D + write16 WTCNT, WTCNT_D + + /* Set clocks */ + write16 FRQCR, FRQCR_D + write16 FRQCR2, FRQCR2_D + + /* Enable all peripherals(Standby Control) */ + write8 STBCR3, STBCR3_D + write8 STBCR4, STBCR4_D + write8 STBCR5, STBCR5_D + write8 STBCR6, STBCR6_D + write8 STBCR7, STBCR7_D + write8 STBCR8, STBCR8_D + write8 STBCR9, STBCR9_D + write8 STBCR10, STBCR10_D + write8 STBCR11, STBCR11_D + write8 STBCR12, STBCR12_D + + /* For serial booting, enable read ahead caching to speed things up */ +#define DRCR_0 0x3FEFA00C + write32 DRCR_0, 0x00010100 /* Read Burst ON, Length=2 */ + + /* Enable all internal RAM */ + write8 SYSCR1, 0xFF + write8 SYSCR2, 0xFF + write8 SYSCR3, 0xFF + + nop + /* back to arch calling code */ + mov pc, lr + + .align 4 diff --git a/board/renesas/grpeach/Makefile b/board/renesas/grpeach/Makefile index 48e185ce3e8..89f8e0e8544 100644 --- a/board/renesas/grpeach/Makefile +++ b/board/renesas/grpeach/Makefile @@ -5,4 +5,3 @@ # SPDX-License-Identifier: GPL-2.0+ obj-y := grpeach.o -obj-y += lowlevel_init.o diff --git a/board/renesas/grpeach/grpeach.c b/board/renesas/grpeach/grpeach.c index 88f65c3b6a0..3a6393fdce1 100644 --- a/board/renesas/grpeach/grpeach.c +++ b/board/renesas/grpeach/grpeach.c @@ -4,17 +4,9 @@ * Copyright (C) Chris Brandt */ -#include #include #include #include -#include -#include - -#define RZA1_WDT_BASE 0xfcfe0000 -#define WTCSR 0x00 -#define WTCNT 0x02 -#define WRCSR 0x04 DECLARE_GLOBAL_DATA_PTR; @@ -39,17 +31,3 @@ int dram_init_banksize(void) return 0; } - -void reset_cpu(void) -{ - /* Dummy read (must read WRCSR:WOVF at least once before clearing) */ - readb(RZA1_WDT_BASE + WRCSR); - - writew(0xa500, RZA1_WDT_BASE + WRCSR); - writew(0x5a5f, RZA1_WDT_BASE + WRCSR); - writew(0x5a00, RZA1_WDT_BASE + WTCNT); - writew(0xa578, RZA1_WDT_BASE + WTCSR); - - for (;;) - asm volatile("wfi"); -} diff --git a/board/renesas/grpeach/lowlevel_init.S b/board/renesas/grpeach/lowlevel_init.S deleted file mode 100644 index b83c4e86867..00000000000 --- a/board/renesas/grpeach/lowlevel_init.S +++ /dev/null @@ -1,106 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Renesas Electronics - * Copyright (C) 2017 Chris Brandt - */ -#include -#include - -/* Watchdog Registers */ -#define RZA1_WDT_BASE 0xFCFE0000 -#define WTCSR (RZA1_WDT_BASE + 0x00) /* Watchdog Timer Control Register */ -#define WTCNT (RZA1_WDT_BASE + 0x02) /* Watchdog Timer Counter Register */ -#define WRCSR (RZA1_WDT_BASE + 0x04) /* Watchdog Reset Control Register */ - -/* Standby controller registers (chapter 55) */ -#define RZA1_STBCR_BASE 0xFCFE0020 -#define STBCR1 (RZA1_STBCR_BASE + 0x00) -#define STBCR2 (RZA1_STBCR_BASE + 0x04) -#define STBCR3 (RZA1_STBCR_BASE + 0x400) -#define STBCR4 (RZA1_STBCR_BASE + 0x404) -#define STBCR5 (RZA1_STBCR_BASE + 0x408) -#define STBCR6 (RZA1_STBCR_BASE + 0x40c) -#define STBCR7 (RZA1_STBCR_BASE + 0x410) -#define STBCR8 (RZA1_STBCR_BASE + 0x414) -#define STBCR9 (RZA1_STBCR_BASE + 0x418) -#define STBCR10 (RZA1_STBCR_BASE + 0x41c) -#define STBCR11 (RZA1_STBCR_BASE + 0x420) -#define STBCR12 (RZA1_STBCR_BASE + 0x424) -#define STBCR13 (RZA1_STBCR_BASE + 0x450) - -/* Clock Registers */ -#define RZA1_FRQCR_BASE 0xFCFE0010 -#define FRQCR (RZA1_FRQCR_BASE + 0x00) -#define FRQCR2 (RZA1_FRQCR_BASE + 0x04) - -#define SYSCR1 0xFCFE0400 /* System control register 1 */ -#define SYSCR2 0xFCFE0404 /* System control register 2 */ -#define SYSCR3 0xFCFE0408 /* System control register 3 */ - -/* Disable WDT */ -#define WTCSR_D 0xA518 -#define WTCNT_D 0x5A00 - -/* Enable all peripheral clocks */ -#define STBCR3_D 0x00000000 -#define STBCR4_D 0x00000000 -#define STBCR5_D 0x00000000 -#define STBCR6_D 0x00000000 -#define STBCR7_D 0x00000024 -#define STBCR8_D 0x00000005 -#define STBCR9_D 0x00000000 -#define STBCR10_D 0x00000000 -#define STBCR11_D 0x000000c0 -#define STBCR12_D 0x000000f0 - -/* - * Set all system clocks to full speed. - * On reset, the CPU will be running at 1/2 speed. - * In the Hardware Manual, see Table 6.3 Settable Frequency Ranges - */ -#define FRQCR_D 0x0035 -#define FRQCR2_D 0x0001 - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - /* PL310 init */ - write32 0x3fffff80, 0x00000001 - - /* Disable WDT */ - write16 WTCSR, WTCSR_D - write16 WTCNT, WTCNT_D - - /* Set clocks */ - write16 FRQCR, FRQCR_D - write16 FRQCR2, FRQCR2_D - - /* Enable all peripherals(Standby Control) */ - write8 STBCR3, STBCR3_D - write8 STBCR4, STBCR4_D - write8 STBCR5, STBCR5_D - write8 STBCR6, STBCR6_D - write8 STBCR7, STBCR7_D - write8 STBCR8, STBCR8_D - write8 STBCR9, STBCR9_D - write8 STBCR10, STBCR10_D - write8 STBCR11, STBCR11_D - write8 STBCR12, STBCR12_D - - /* For serial booting, enable read ahead caching to speed things up */ -#define DRCR_0 0x3FEFA00C - write32 DRCR_0, 0x00010100 /* Read Burst ON, Length=2 */ - - /* Enable all internal RAM */ - write8 SYSCR1, 0xFF - write8 SYSCR2, 0xFF - write8 SYSCR3, 0xFF - - nop - /* back to arch calling code */ - mov pc, lr - - .align 4 -- cgit v1.2.3 From 25adecf09467c6a2823bcdfaf3fb0b59b2389669 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 2 Jul 2025 19:13:54 +0200 Subject: ARM: renesas: Add support for the r7s72100 Genmai board Add r7s72100 Genmai board support. Serial console, NOR Flash and Ethernet are known to work however on-board SDRAM is not yet enabled. Signed-off-by: Magnus Damm --- arch/arm/dts/Makefile | 1 + arch/arm/dts/r7s72100-genmai-u-boot.dtsi | 32 +++++++++++++++++++++ arch/arm/mach-renesas/Kconfig.rza1 | 4 +++ board/renesas/genmai/Kconfig | 12 ++++++++ board/renesas/genmai/MAINTAINERS | 5 ++++ board/renesas/genmai/Makefile | 7 +++++ board/renesas/genmai/genmai.c | 49 ++++++++++++++++++++++++++++++++ configs/genmai_defconfig | 17 +++++++++++ include/configs/genmai.h | 15 ++++++++++ 9 files changed, 142 insertions(+) create mode 100644 arch/arm/dts/r7s72100-genmai-u-boot.dtsi create mode 100644 board/renesas/genmai/Kconfig create mode 100644 board/renesas/genmai/MAINTAINERS create mode 100644 board/renesas/genmai/Makefile create mode 100644 board/renesas/genmai/genmai.c create mode 100644 configs/genmai_defconfig create mode 100644 include/configs/genmai.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 10404ce076e..17795f8f746 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -924,6 +924,7 @@ dtb-$(CONFIG_ARCH_IMXRT) += imxrt1020-evk.dtb \ imxrt1170-evk.dtb \ dtb-$(CONFIG_RZA1) += \ + r7s72100-genmai.dtb \ r7s72100-gr-peach.dtb dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb diff --git a/arch/arm/dts/r7s72100-genmai-u-boot.dtsi b/arch/arm/dts/r7s72100-genmai-u-boot.dtsi new file mode 100644 index 00000000000..782ebfea2fb --- /dev/null +++ b/arch/arm/dts/r7s72100-genmai-u-boot.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot for the Genmai board + * Based on GR Peach, Copyright (C) 2019 Marek Vasut + */ + +/ { + soc { + bootph-all; + }; +}; + +&bsc { + bootph-all; +}; + +&ostm0 { + bootph-all; +}; + +&pinctrl { + bootph-all; +}; + +&scif2 { + bootph-all; + clock = <66666666>; /* ToDo: Replace by DM clock driver */ +}; + +&scif2_pins { + bootph-all; +}; diff --git a/arch/arm/mach-renesas/Kconfig.rza1 b/arch/arm/mach-renesas/Kconfig.rza1 index e88f9a2eedb..c9e2b835204 100644 --- a/arch/arm/mach-renesas/Kconfig.rza1 +++ b/arch/arm/mach-renesas/Kconfig.rza1 @@ -14,12 +14,16 @@ choice prompt "Renesas RZ/A1 board select" # Renesas Supported Boards +config TARGET_GENMAI + bool "GENMAI board" + config TARGET_GRPEACH bool "GR-PEACH board" endchoice # Renesas Supported Boards +source "board/renesas/genmai/Kconfig" source "board/renesas/grpeach/Kconfig" endif diff --git a/board/renesas/genmai/Kconfig b/board/renesas/genmai/Kconfig new file mode 100644 index 00000000000..4e67a9b325a --- /dev/null +++ b/board/renesas/genmai/Kconfig @@ -0,0 +1,12 @@ +if TARGET_GENMAI + +config SYS_BOARD + default "genmai" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "genmai" + +endif diff --git a/board/renesas/genmai/MAINTAINERS b/board/renesas/genmai/MAINTAINERS new file mode 100644 index 00000000000..1f1c2944632 --- /dev/null +++ b/board/renesas/genmai/MAINTAINERS @@ -0,0 +1,5 @@ +GENMAI BOARD +M: Magnus Damm +S: Maintained +F: arch/arm/dts/r7s72100* +N: genmai diff --git a/board/renesas/genmai/Makefile b/board/renesas/genmai/Makefile new file mode 100644 index 00000000000..73f5e45affd --- /dev/null +++ b/board/renesas/genmai/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2025 Magnus Damm +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := genmai.o diff --git a/board/renesas/genmai/genmai.c b/board/renesas/genmai/genmai.c new file mode 100644 index 00000000000..8153aed15e3 --- /dev/null +++ b/board/renesas/genmai/genmai.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Magnus Damm + */ + +#include +#include +#include + +#define RZA1_BCR_BASE 0x3FFFC000 +#define CS0BCR (RZA1_BCR_BASE + 0x04) +#define CS0WCR (RZA1_BCR_BASE + 0x28) +#define CS1BCR (RZA1_BCR_BASE + 0x08) +#define CS1WCR (RZA1_BCR_BASE + 0x2c) + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; + + /* setup NOR Flash on CS0 and CS1 */ + writel(0x00000b40, CS0WCR); + writel(0x10000c00, CS0BCR); + writel(0x00000b40, CS1WCR); + writel(0x10000c00, CS1BCR); + return 0; +} + +/* + * The Genmai DT will most likely contain memory nodes describing the external + * SDRAM memory connected to CS2 and CS3, however we do not yet have any code + * in U-Boot to setup the memory controller. For now ignore DT and make use of + * the RZ/A1H on-chip memory which is 10 MiB at CFG_SYS_SDRAM_BASE. + */ + +int dram_init(void) +{ + gd->ram_base = CFG_SYS_SDRAM_BASE; + gd->ram_size = 10 << 20; + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = gd->ram_base; + gd->bd->bi_dram[0].size = gd->ram_size; + return 0; +} diff --git a/configs/genmai_defconfig b/configs/genmai_defconfig new file mode 100644 index 00000000000..d3407f671e2 --- /dev/null +++ b/configs/genmai_defconfig @@ -0,0 +1,17 @@ +#include + +CONFIG_ARM=y +CONFIG_ARCH_RENESAS=y +CONFIG_TEXT_BASE=0x00000000 +CONFIG_POSITION_INDEPENDENT=y +CONFIG_DEFAULT_DEVICE_TREE="renesas/r7s72100-genmai" +CONFIG_TARGET_GENMAI=y + +CONFIG_ENV_IS_IN_MTD=y +CONFIG_ENV_MTD_DEV="nor0" +CONFIG_ENV_OFFSET=0x80000 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_MTD=y +CONFIG_SYS_MAX_FLASH_BANKS=2 diff --git a/include/configs/genmai.h b/include/configs/genmai.h new file mode 100644 index 00000000000..1d43f8e06af --- /dev/null +++ b/include/configs/genmai.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration settings for the Renesas GENMAI board + * + * Copyright (C) 2017-2019 Renesas Electronics + */ + +#ifndef __GENMAI_H +#define __GENMAI_H + +/* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */ +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE (10 * 1024 * 1024) + +#endif /* __GENAMI_H */ -- cgit v1.2.3