From d91796f4d92e3d015eb2ddbca88d01f97a8ea76a Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Fri, 24 Oct 2014 14:41:41 +0200 Subject: colibri_vf: use PLL1 as DDR clock on VF50 On VF50, we can use PLL1 as DDR clock since the CPU is clocked with 400MHz as well. This saves some power (measured around ~10mW). --- board/toradex/colibri_vf/colibri_vf.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index 5e990553f9..cef2e50f24 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -153,7 +153,7 @@ static void clock_init(void) { struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; - u32 pfd_clk_sel; + u32 pfd_clk_sel, ddr_clk_sel; clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, CCM_CCGR0_UART0_CTRL_MASK); @@ -180,9 +180,12 @@ static void clock_init(void) clrsetbits_le32(&anadig->pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS | ANADIG_PLL5_CTRL_POWERDOWN, ANADIG_PLL5_CTRL_ENABLE | ANADIG_PLL5_CTRL_DIV_SELECT); - clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL5_CTRL_BYPASS | - ANADIG_PLL2_CTRL_POWERDOWN, ANADIG_PLL2_CTRL_ENABLE | - ANADIG_PLL2_CTRL_DIV_SELECT); + + if (is_colibri_vf61()) { + clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL5_CTRL_BYPASS | + ANADIG_PLL2_CTRL_POWERDOWN, ANADIG_PLL2_CTRL_ENABLE | + ANADIG_PLL2_CTRL_DIV_SELECT); + } clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN, ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT); @@ -192,15 +195,20 @@ static void clock_init(void) CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5)); /* See "Typical PLL Configuration" */ - pfd_clk_sel = is_colibri_vf61() ? CCM_CCSR_PLL1_PFD_CLK_SEL(1) : - CCM_CCSR_PLL1_PFD_CLK_SEL(3); + if (is_colibri_vf61()) { + pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(1); + ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(0); + } else { + pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(3); + ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(1); + } clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, pfd_clk_sel | CCM_CCSR_PLL2_PFD4_EN | CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN | CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN | CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN | CCM_CCSR_PLL1_PFD1_EN | - CCM_CCSR_FAST_CLK_SEL(1) | + ddr_clk_sel | CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4)); clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK, -- cgit v1.2.3