From 0b868589563ab96384b9a817bc5b82d93c573ea5 Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Wed, 9 Jul 2014 19:48:40 +0300 Subject: keystone: ddr3: add ddr3.h to hold ddr3 API It's convinient to hold ddr3 function definitions in separate file such as ddr3.h. So move this from hardware.h to ddr3.h. Acked-by: Murali Karicheri Signed-off-by: Ivan Khoronzhuk --- arch/arm/cpu/armv7/keystone/ddr3.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm/cpu/armv7/keystone/ddr3.c') diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c b/arch/arm/cpu/armv7/keystone/ddr3.c index 4875db76a35..bb16551eb2c 100644 --- a/arch/arm/cpu/armv7/keystone/ddr3.c +++ b/arch/arm/cpu/armv7/keystone/ddr3.c @@ -7,10 +7,10 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include #include +#include -void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) +void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) { unsigned int tmp; @@ -57,7 +57,7 @@ void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) ; } -void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg) +void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg) { __raw_writel(emif_cfg->sdcfg, base + KS2_DDR3_SDCFG_OFFSET); __raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET); -- cgit v1.2.3 From 101eec50f021a354487a511dc1f72691404b2b48 Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Wed, 9 Jul 2014 19:48:41 +0300 Subject: keystone2: ddr: add DDR3 PHY configs updated for PG 2.0 Add DDR3 PHY configs updated for PG 2.0 Also add DDR3A PHY reset before init for PG2.0 SoCs. Acked-by: Murali Karicheri Signed-off-by: Hao Zhang Signed-off-by: Ivan Khoronzhuk --- arch/arm/cpu/armv7/keystone/ddr3.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm/cpu/armv7/keystone/ddr3.c') diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c b/arch/arm/cpu/armv7/keystone/ddr3.c index bb16551eb2c..b711b810cbd 100644 --- a/arch/arm/cpu/armv7/keystone/ddr3.c +++ b/arch/arm/cpu/armv7/keystone/ddr3.c @@ -8,6 +8,7 @@ */ #include +#include #include void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) @@ -67,3 +68,21 @@ void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg) __raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET); __raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET); } + +void ddr3_reset_ddrphy(void) +{ + u32 tmp; + + /* Assert DDR3A PHY reset */ + tmp = readl(K2HK_DDR3APLLCTL1); + tmp |= KS2_DDR3_PLLCTRL_PHY_RESET; + writel(tmp, K2HK_DDR3APLLCTL1); + + /* wait 10us to catch the reset */ + udelay(10); + + /* Release DDR3A PHY reset */ + tmp = readl(K2HK_DDR3APLLCTL1); + tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET; + __raw_writel(tmp, K2HK_DDR3APLLCTL1); +} -- cgit v1.2.3 From 3d315386255f6d944c0ccb4c7c8819ce604429ab Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Wed, 9 Jul 2014 23:44:44 +0300 Subject: k2hk: use common KS2_ prefix for all hardware definitions Use KS2_ prefix in all definitions, for that replace K2HK_ prefix and add KS2_ prefix where it's needed. It requires to change names also in places where they're used. Align lines and remove redundant definitions in kardware-k2hk.h at the same time. Using common KS2_ prefix helps resolve redundant redefinitions and adds opportunity to use KS2_ definition across a project not thinking about what SoC should be used. It's more convenient and we don't need to worry about the SoC type in common files, hardware.h will think about that. The hardware.h decides definitions of what SoC to use. Acked-by: Murali Karicheri Signed-off-by: Ivan Khoronzhuk --- arch/arm/cpu/armv7/keystone/ddr3.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm/cpu/armv7/keystone/ddr3.c') diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c b/arch/arm/cpu/armv7/keystone/ddr3.c index b711b810cbd..2391e794e89 100644 --- a/arch/arm/cpu/armv7/keystone/ddr3.c +++ b/arch/arm/cpu/armv7/keystone/ddr3.c @@ -74,15 +74,15 @@ void ddr3_reset_ddrphy(void) u32 tmp; /* Assert DDR3A PHY reset */ - tmp = readl(K2HK_DDR3APLLCTL1); + tmp = readl(KS2_DDR3APLLCTL1); tmp |= KS2_DDR3_PLLCTRL_PHY_RESET; - writel(tmp, K2HK_DDR3APLLCTL1); + writel(tmp, KS2_DDR3APLLCTL1); /* wait 10us to catch the reset */ udelay(10); /* Release DDR3A PHY reset */ - tmp = readl(K2HK_DDR3APLLCTL1); + tmp = readl(KS2_DDR3APLLCTL1); tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET; - __raw_writel(tmp, K2HK_DDR3APLLCTL1); + __raw_writel(tmp, KS2_DDR3APLLCTL1); } -- cgit v1.2.3