From 2f78eae5064728d6cd907148cfeaf8ba3e63b0ef Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 23 Jun 2014 15:15:54 -0700 Subject: ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun Signed-off-by: Varun Sethi Signed-off-by: Arnab Basu --- arch/arm/cpu/armv8/cache_v8.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/arm/cpu/armv8/cache_v8.c') diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index af3c4945ecb..9dbcdf22afe 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -73,12 +73,17 @@ void invalidate_dcache_all(void) __asm_invalidate_dcache_all(); } +void __weak flush_l3_cache(void) +{ +} + /* * Performs a clean & invalidation of the entire data cache at all levels */ void flush_dcache_all(void) { __asm_flush_dcache_all(); + flush_l3_cache(); } /* @@ -211,7 +216,7 @@ void invalidate_icache_all(void) * Enable dCache & iCache, whether cache is actually enabled * depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF */ -void enable_caches(void) +void __weak enable_caches(void) { icache_enable(); dcache_enable(); -- cgit v1.2.3