From 43620a954fe13be0df835cd37866957057ab78df Mon Sep 17 00:00:00 2001 From: Hari Nagalla Date: Fri, 26 May 2023 10:32:59 -0500 Subject: arm: dts: Add R5F device node for AM62A AM62A devices have a single core R5F processor in MCU volatage domain. The MCU domain also has a 512KB SRAM, which can be used by R5F core. Signed-off-by: Hari Nagalla --- arch/arm/dts/k3-am62a-mcu.dtsi | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'arch/arm/dts/k3-am62a-mcu.dtsi') diff --git a/arch/arm/dts/k3-am62a-mcu.dtsi b/arch/arm/dts/k3-am62a-mcu.dtsi index 6d1e501b94..a3d43bfa9c 100644 --- a/arch/arm/dts/k3-am62a-mcu.dtsi +++ b/arch/arm/dts/k3-am62a-mcu.dtsi @@ -6,6 +6,18 @@ */ &cbass_mcu { + mcu_ram: sram@79100000 { + compatible = "mmio-sram"; + reg = <0x00 0x79100000 0x00 0x80000>; + ranges = <0x00 0x00 0x79100000 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + + mcu_sram1@0 { + reg = <0x0 0x80000>; + }; + }; + mcu_pmx0: pinctrl@4084000 { compatible = "pinctrl-single"; reg = <0x00 0x04084000 0x00 0x88>; @@ -36,4 +48,30 @@ clock-names = "fck"; status = "disabled"; }; + + mcu_r5fss0: r5fss@79000000 { + compatible = "ti,am62-r5fss"; + ti,cluster-mode = <0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x79000000 0x00 0x79000000 0x8000>, + <0x79020000 0x00 0x79020000 0x8000>; + power-domains = <&k3_pds 7 TI_SCI_PD_EXCLUSIVE>; + + mcu_r5fss0_core0: r5f@79000000 { + compatible = "ti,am62-r5f"; + reg = <0x79000000 0x00008000>, + <0x79020000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <9>; + ti,sci-proc-ids = <0x03 0xff>; + resets = <&k3_reset 9 1>; + firmware-name = "am62-mcu-r5f0_0-fw"; + ti,atcm-enable = <0>; + ti,btcm-enable = <1>; + ti,loczrama = <0>; + sram = <&mcu_ram>; + }; + }; }; -- cgit v1.2.3