From 382230dc8b04fd4d3282223bc63609044ec16346 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 11 Oct 2011 09:46:22 -0700 Subject: tegra: Correct GPIO definitions for Tegra2 The GPIO definitions for Tegra2 were incorrectly matched up with Tegra2. The layout is actually different, so GPIOs beyond port D do not work. This separates out the GPIO headers again, so that Tegra2 and Tegra3 have separate structure definitions. BUG=None TEST='vboot_test gpio' on Kaen; see that it responds to google rec, power, lid correctly Change-Id: I8540a87c8faa7179c8f0d44ef3f18b3c576392cc Signed-off-by: Simon Glass Reviewed-on: http://gerrit.chromium.org/gerrit/9847 Reviewed-by: Bryan Freed Tested-by: Bryan Freed --- arch/arm/include/asm/arch-tegra3/gpio.h | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) (limited to 'arch/arm/include/asm/arch-tegra3') diff --git a/arch/arm/include/asm/arch-tegra3/gpio.h b/arch/arm/include/asm/arch-tegra3/gpio.h index 4febdcf12d..4035b6bd30 100644 --- a/arch/arm/include/asm/arch-tegra3/gpio.h +++ b/arch/arm/include/asm/arch-tegra3/gpio.h @@ -24,11 +24,37 @@ #define CONFIG_TEGRA_MAX_GPIO_PORT 30 /* GPIO_PEEx */ +#include + /* * The Tegra 3x GPIO controller has 246 GPIOs arranged in 8 banks of 4 ports, * each with 8 GPIOs. */ -#include + +/* GPIO Controller registers for a single bank */ +struct gpio_ctlr_bank { + uint gpio_config[TEGRA_GPIO_PORTS]; + uint gpio_dir_out[TEGRA_GPIO_PORTS]; + uint gpio_out[TEGRA_GPIO_PORTS]; + uint gpio_in[TEGRA_GPIO_PORTS]; + uint gpio_int_status[TEGRA_GPIO_PORTS]; + uint gpio_int_enable[TEGRA_GPIO_PORTS]; + uint gpio_int_level[TEGRA_GPIO_PORTS]; + uint gpio_int_clear[TEGRA_GPIO_PORTS]; + + uint gpio_masked_config[TEGRA_GPIO_PORTS]; + uint gpio_masked_dir_out[TEGRA_GPIO_PORTS]; + uint gpio_masked_out[TEGRA_GPIO_PORTS]; + uint gpio_masked_in[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_status[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_enable[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_level[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_clear[TEGRA_GPIO_PORTS]; +}; + +struct gpio_ctlr { + struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; +}; #define GPIO_PCC0 224 #define GPIO_PCC1 225 -- cgit v1.2.3