From dfa41387155daed35cc6b294b2390641aa887a1d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Stehl=C3=A9?= Date: Mon, 4 Mar 2013 20:04:43 +0000 Subject: ARM: cache: declare set_section_dcache MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We declare the set_section_dcache function globally in the cache header, for later use by e.g. machine specific code. Signed-off-by: Vincent Stehlé ti.com> Cc: Tom Rini ti.com> Cc: Albert ARIBAUD --- arch/arm/include/asm/cache.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include/asm/cache.h') diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index eef6a5a8f23..416d2c8f937 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -41,6 +41,7 @@ static inline void invalidate_l2_cache(void) void l2_cache_enable(void); void l2_cache_disable(void); +void set_section_dcache(int section, enum dcache_option option); /* * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We -- cgit v1.2.3 From 96fdbec2f96c9e11758c8742409069eeef841722 Mon Sep 17 00:00:00 2001 From: R Sricharan Date: Mon, 4 Mar 2013 20:04:44 +0000 Subject: ARM: mmu: Introduce weak dram_bank_setup function Introduce a weak version of dram_bank_setup function to allow a platform specific function. This is used in the subsequent patch to setup dram region without 'XN' attribute in order to enable the region under client permissions. Signed-off-by: R Sricharan Cc: Vincent Stehle Cc: Tom Rini Cc: Albert ARIBAUD --- arch/arm/include/asm/cache.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include/asm/cache.h') diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index 416d2c8f937..81534848991 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -43,6 +43,7 @@ void l2_cache_enable(void); void l2_cache_disable(void); void set_section_dcache(int section, enum dcache_option option); +void dram_bank_mmu_setup(int bank); /* * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We * use that value for aligning DMA buffers unless the board config has specified -- cgit v1.2.3