From 6c70935d7525a4b2b144b49457d2bae85f1d111a Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Fri, 8 Nov 2013 17:40:37 +0530 Subject: ARM: DRA: EMIF: Change DDR3 settings to use hw leveling Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using software leveling. This was done since hardware leveling was not working. Now that the right sequence to do hw leveling is identified, use it. This is required for EMIF clockdomain to idle and come back during lowpower usecases. Signed-off-by: Sricharan R --- arch/arm/include/asm/emif.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/arm/include/asm/emif.h') diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 1b94a99c54d..c12beea0cab 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -581,7 +581,6 @@ (0xFF << EMIF_SYS_ADDR_SHIFT)) #define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5 -#define EMIF_EXT_PHY_CTRL_CONST_REG 0x14 /* Reg mapping structure */ struct emif_reg_struct { @@ -690,6 +689,9 @@ struct emif_reg_struct { u32 emif_ddr_ext_phy_ctrl_23_shdw; u32 emif_ddr_ext_phy_ctrl_24; u32 emif_ddr_ext_phy_ctrl_24_shdw; + u32 padding[22]; + u32 emif_ddr_fifo_misaligned_clear_1; + u32 emif_ddr_fifo_misaligned_clear_2; }; struct dmm_lisa_map_regs { -- cgit v1.2.3 From 54d022e76c42d824315e28ea06c89c2452f98861 Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Fri, 8 Nov 2013 17:40:38 +0530 Subject: ARM: DRA7/OMAP5: EMIF: Add workaround for bug 0039 When core power domain hits oswr, then DDR3 memories does not come back while resuming. This is because when EMIF registers are lost, then the controller takes care of copying the values from the shadow registers. If the shadow registers are not updated with the right values, then this results in incorrect settings while resuming. So updating the shadow registers with the corresponding status registers here during the boot. Signed-off-by: Sricharan R --- arch/arm/include/asm/emif.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'arch/arm/include/asm/emif.h') diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index c12beea0cab..d9d521a5150 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -640,7 +640,9 @@ struct emif_reg_struct { u32 emif_ddr_phy_ctrl_2; u32 padding7[12]; u32 emif_rd_wr_exec_thresh; - u32 padding8[55]; + u32 padding8[7]; + u32 emif_ddr_phy_status[21]; + u32 padding9[27]; u32 emif_ddr_ext_phy_ctrl_1; u32 emif_ddr_ext_phy_ctrl_1_shdw; u32 emif_ddr_ext_phy_ctrl_2; @@ -1141,6 +1143,11 @@ struct lpddr2_mr_regs { s8 mr16; }; +struct read_write_regs { + u32 read_reg; + u32 write_reg; +}; + /* assert macros */ #if defined(DEBUG) #define emif_assert(c) ({ if (!(c)) for (;;); }) @@ -1169,4 +1176,5 @@ extern u32 *const T_den; void config_data_eye_leveling_samples(u32 emif_base); u32 emif_sdram_type(void); +const struct read_write_regs *get_bug_regs(u32 *iterations); #endif -- cgit v1.2.3