From f660fe0bd3a8cfa7fc6271bbf27b1530e7348b85 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 11 Feb 2022 11:29:38 +0000 Subject: armv8: Simplify switch_el macro The switch_el macro is a neat contraption to handle cases where we need different code depending on the current exception level, but its implementation was longer than needed. Simplify it by doing just one comparison, then using the different condition codes to branch to the desired target. PState.CurrentEL just holds two bits, and since we don't care about EL0, we can use >, =, < to select EL3, EL2 and EL1, respectively. Signed-off-by: Andre Przywara --- arch/arm/include/asm/macro.h | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'arch/arm/include/asm/macro.h') diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h index ec0171e0e6c..acd519020d7 100644 --- a/arch/arm/include/asm/macro.h +++ b/arch/arm/include/asm/macro.h @@ -69,12 +69,10 @@ lr .req x30 */ .macro switch_el, xreg, el3_label, el2_label, el1_label mrs \xreg, CurrentEL - cmp \xreg, 0xc - b.eq \el3_label - cmp \xreg, 0x8 + cmp \xreg, #0x8 + b.gt \el3_label b.eq \el2_label - cmp \xreg, 0x4 - b.eq \el1_label + b.lt \el1_label .endm /* -- cgit v1.2.3 From 5ff4857d3569710c0f1ce1848f1e7486e3a4cfbe Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 11 Feb 2022 11:29:39 +0000 Subject: armv8: Fix and simplify branch_if_master/branch_if_slave The branch_if_master macro jumps to a label if the CPU is the "master" core, which we define as having all affinity levels set to 0. To check for this condition, we need to mask off some bits from the MPIDR register, then compare the remaining register value against zero. The implementation of this was slighly broken (it preserved the upper RES0 bits), overly complicated and hard to understand, especially since it lacked comments. The same was true for the very similar branch_if_slave macro. Use a much shorter assembly sequence for those checks, use the same masking for both macros (just negate the final branch), and put some comments on them, to make it clear what the code does. This allows to drop the second temporary register for branch_if_master, so we adjust all call sites as well. Also use the opportunity to remove a misleading comment: the macro works fine on SoCs with multiple clusters. Judging by the commit message, the original problem with the Juno SoC stems from the fact that the master CPU *can* be configured to be from cluster 1, so the assumption that the master CPU has all affinity values set to 0 does not hold there. But this is already mentioned above in a comment, so remove the extra comment. Signed-off-by: Andre Przywara --- arch/arm/include/asm/macro.h | 29 ++++++++--------------------- 1 file changed, 8 insertions(+), 21 deletions(-) (limited to 'arch/arm/include/asm/macro.h') diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h index acd519020d7..1a1edc98703 100644 --- a/arch/arm/include/asm/macro.h +++ b/arch/arm/include/asm/macro.h @@ -121,19 +121,10 @@ lr .req x30 */ .macro branch_if_slave, xreg, slave_label #ifdef CONFIG_ARMV8_MULTIENTRY - /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */ mrs \xreg, mpidr_el1 - tst \xreg, #0xff /* Test Affinity 0 */ - b.ne \slave_label - lsr \xreg, \xreg, #8 - tst \xreg, #0xff /* Test Affinity 1 */ - b.ne \slave_label - lsr \xreg, \xreg, #8 - tst \xreg, #0xff /* Test Affinity 2 */ - b.ne \slave_label - lsr \xreg, \xreg, #16 - tst \xreg, #0xff /* Test Affinity 3 */ - b.ne \slave_label + and \xreg, \xreg, 0xffffffffff /* clear bits [63:40] */ + and \xreg, \xreg, ~0x00ff000000 /* also clear bits [31:24] */ + cbnz \xreg, \slave_label #endif .endm @@ -141,16 +132,12 @@ lr .req x30 * Branch if current processor is a master, * choose processor with all zero affinity value as the master. */ -.macro branch_if_master, xreg1, xreg2, master_label +.macro branch_if_master, xreg, master_label #ifdef CONFIG_ARMV8_MULTIENTRY - /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */ - mrs \xreg1, mpidr_el1 - lsr \xreg2, \xreg1, #32 - lsl \xreg2, \xreg2, #32 - lsl \xreg1, \xreg1, #40 - lsr \xreg1, \xreg1, #40 - orr \xreg1, \xreg1, \xreg2 - cbz \xreg1, \master_label + mrs \xreg, mpidr_el1 + and \xreg, \xreg, 0xffffffffff /* clear bits [63:40] */ + and \xreg, \xreg, ~0x00ff000000 /* also clear bits [31:24] */ + cbz \xreg, \master_label #else b \master_label #endif -- cgit v1.2.3