From 01b753ff7badb5b8670794de3d5dd71e1c4c9baf Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Mon, 4 Feb 2013 04:22:00 +0000 Subject: ARM: OMAP4+: Change the PRCM structure prototype common for all Socs The current PRCM structure prototype directly matches the hardware register layout. So there is a need to change this for every new silicon revision which has register space changes. Avoiding this by making the prototye generic and populating the register addresses seperately for all Socs. Signed-off-by: R Sricharan Signed-off-by: Lokesh Vutla --- arch/arm/include/asm/omap_common.h | 304 +++++++++++++++++++++++++++++++++++++ 1 file changed, 304 insertions(+) (limited to 'arch/arm/include/asm/omap_common.h') diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 2a40b898e35..fcf9ce50d62 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -25,6 +25,310 @@ #ifndef _OMAP_COMMON_H_ #define _OMAP_COMMON_H_ +#include + +struct prcm_regs { + /* cm1.ckgen */ + u32 cm_clksel_core; + u32 cm_clksel_abe; + u32 cm_dll_ctrl; + u32 cm_clkmode_dpll_core; + u32 cm_idlest_dpll_core; + u32 cm_autoidle_dpll_core; + u32 cm_clksel_dpll_core; + u32 cm_div_m2_dpll_core; + u32 cm_div_m3_dpll_core; + u32 cm_div_h11_dpll_core; + u32 cm_div_h12_dpll_core; + u32 cm_div_h13_dpll_core; + u32 cm_div_h14_dpll_core; + u32 cm_ssc_deltamstep_dpll_core; + u32 cm_ssc_modfreqdiv_dpll_core; + u32 cm_emu_override_dpll_core; + u32 cm_div_h22_dpllcore; + u32 cm_div_h23_dpll_core; + u32 cm_clkmode_dpll_mpu; + u32 cm_idlest_dpll_mpu; + u32 cm_autoidle_dpll_mpu; + u32 cm_clksel_dpll_mpu; + u32 cm_div_m2_dpll_mpu; + u32 cm_ssc_deltamstep_dpll_mpu; + u32 cm_ssc_modfreqdiv_dpll_mpu; + u32 cm_bypclk_dpll_mpu; + u32 cm_clkmode_dpll_iva; + u32 cm_idlest_dpll_iva; + u32 cm_autoidle_dpll_iva; + u32 cm_clksel_dpll_iva; + u32 cm_div_h11_dpll_iva; + u32 cm_div_h12_dpll_iva; + u32 cm_ssc_deltamstep_dpll_iva; + u32 cm_ssc_modfreqdiv_dpll_iva; + u32 cm_bypclk_dpll_iva; + u32 cm_clkmode_dpll_abe; + u32 cm_idlest_dpll_abe; + u32 cm_autoidle_dpll_abe; + u32 cm_clksel_dpll_abe; + u32 cm_div_m2_dpll_abe; + u32 cm_div_m3_dpll_abe; + u32 cm_ssc_deltamstep_dpll_abe; + u32 cm_ssc_modfreqdiv_dpll_abe; + u32 cm_clkmode_dpll_ddrphy; + u32 cm_idlest_dpll_ddrphy; + u32 cm_autoidle_dpll_ddrphy; + u32 cm_clksel_dpll_ddrphy; + u32 cm_div_m2_dpll_ddrphy; + u32 cm_div_h11_dpll_ddrphy; + u32 cm_div_h12_dpll_ddrphy; + u32 cm_div_h13_dpll_ddrphy; + u32 cm_ssc_deltamstep_dpll_ddrphy; + u32 cm_shadow_freq_config1; + u32 cm_mpu_mpu_clkctrl; + + /* cm1.dsp */ + u32 cm_dsp_clkstctrl; + u32 cm_dsp_dsp_clkctrl; + + /* cm1.abe */ + u32 cm1_abe_clkstctrl; + u32 cm1_abe_l4abe_clkctrl; + u32 cm1_abe_aess_clkctrl; + u32 cm1_abe_pdm_clkctrl; + u32 cm1_abe_dmic_clkctrl; + u32 cm1_abe_mcasp_clkctrl; + u32 cm1_abe_mcbsp1_clkctrl; + u32 cm1_abe_mcbsp2_clkctrl; + u32 cm1_abe_mcbsp3_clkctrl; + u32 cm1_abe_slimbus_clkctrl; + u32 cm1_abe_timer5_clkctrl; + u32 cm1_abe_timer6_clkctrl; + u32 cm1_abe_timer7_clkctrl; + u32 cm1_abe_timer8_clkctrl; + u32 cm1_abe_wdt3_clkctrl; + + /* cm2.ckgen */ + u32 cm_clksel_mpu_m3_iss_root; + u32 cm_clksel_usb_60mhz; + u32 cm_scale_fclk; + u32 cm_core_dvfs_perf1; + u32 cm_core_dvfs_perf2; + u32 cm_core_dvfs_perf3; + u32 cm_core_dvfs_perf4; + u32 cm_core_dvfs_current; + u32 cm_iva_dvfs_perf_tesla; + u32 cm_iva_dvfs_perf_ivahd; + u32 cm_iva_dvfs_perf_abe; + u32 cm_iva_dvfs_current; + u32 cm_clkmode_dpll_per; + u32 cm_idlest_dpll_per; + u32 cm_autoidle_dpll_per; + u32 cm_clksel_dpll_per; + u32 cm_div_m2_dpll_per; + u32 cm_div_m3_dpll_per; + u32 cm_div_h11_dpll_per; + u32 cm_div_h12_dpll_per; + u32 cm_div_h14_dpll_per; + u32 cm_ssc_deltamstep_dpll_per; + u32 cm_ssc_modfreqdiv_dpll_per; + u32 cm_emu_override_dpll_per; + u32 cm_clkmode_dpll_usb; + u32 cm_idlest_dpll_usb; + u32 cm_autoidle_dpll_usb; + u32 cm_clksel_dpll_usb; + u32 cm_div_m2_dpll_usb; + u32 cm_ssc_deltamstep_dpll_usb; + u32 cm_ssc_modfreqdiv_dpll_usb; + u32 cm_clkdcoldo_dpll_usb; + u32 cm_clkmode_dpll_unipro; + u32 cm_idlest_dpll_unipro; + u32 cm_autoidle_dpll_unipro; + u32 cm_clksel_dpll_unipro; + u32 cm_div_m2_dpll_unipro; + u32 cm_ssc_deltamstep_dpll_unipro; + u32 cm_ssc_modfreqdiv_dpll_unipro; + + /* cm2.core */ + u32 cm_coreaon_bandgap_clkctrl; + u32 cm_l3_1_clkstctrl; + u32 cm_l3_1_dynamicdep; + u32 cm_l3_1_l3_1_clkctrl; + u32 cm_l3_2_clkstctrl; + u32 cm_l3_2_dynamicdep; + u32 cm_l3_2_l3_2_clkctrl; + u32 cm_l3_2_gpmc_clkctrl; + u32 cm_l3_2_ocmc_ram_clkctrl; + u32 cm_mpu_m3_clkstctrl; + u32 cm_mpu_m3_staticdep; + u32 cm_mpu_m3_dynamicdep; + u32 cm_mpu_m3_mpu_m3_clkctrl; + u32 cm_sdma_clkstctrl; + u32 cm_sdma_staticdep; + u32 cm_sdma_dynamicdep; + u32 cm_sdma_sdma_clkctrl; + u32 cm_memif_clkstctrl; + u32 cm_memif_dmm_clkctrl; + u32 cm_memif_emif_fw_clkctrl; + u32 cm_memif_emif_1_clkctrl; + u32 cm_memif_emif_2_clkctrl; + u32 cm_memif_dll_clkctrl; + u32 cm_memif_emif_h1_clkctrl; + u32 cm_memif_emif_h2_clkctrl; + u32 cm_memif_dll_h_clkctrl; + u32 cm_c2c_clkstctrl; + u32 cm_c2c_staticdep; + u32 cm_c2c_dynamicdep; + u32 cm_c2c_sad2d_clkctrl; + u32 cm_c2c_modem_icr_clkctrl; + u32 cm_c2c_sad2d_fw_clkctrl; + u32 cm_l4cfg_clkstctrl; + u32 cm_l4cfg_dynamicdep; + u32 cm_l4cfg_l4_cfg_clkctrl; + u32 cm_l4cfg_hw_sem_clkctrl; + u32 cm_l4cfg_mailbox_clkctrl; + u32 cm_l4cfg_sar_rom_clkctrl; + u32 cm_l3instr_clkstctrl; + u32 cm_l3instr_l3_3_clkctrl; + u32 cm_l3instr_l3_instr_clkctrl; + u32 cm_l3instr_intrconn_wp1_clkctrl; + + /* cm2.ivahd */ + u32 cm_ivahd_clkstctrl; + u32 cm_ivahd_ivahd_clkctrl; + u32 cm_ivahd_sl2_clkctrl; + + /* cm2.cam */ + u32 cm_cam_clkstctrl; + u32 cm_cam_iss_clkctrl; + u32 cm_cam_fdif_clkctrl; + + /* cm2.dss */ + u32 cm_dss_clkstctrl; + u32 cm_dss_dss_clkctrl; + + /* cm2.sgx */ + u32 cm_sgx_clkstctrl; + u32 cm_sgx_sgx_clkctrl; + + /* cm2.l3init */ + u32 cm_l3init_clkstctrl; + + /* cm2.l3init */ + u32 cm_l3init_hsmmc1_clkctrl; + u32 cm_l3init_hsmmc2_clkctrl; + u32 cm_l3init_hsi_clkctrl; + u32 cm_l3init_hsusbhost_clkctrl; + u32 cm_l3init_hsusbotg_clkctrl; + u32 cm_l3init_hsusbtll_clkctrl; + u32 cm_l3init_p1500_clkctrl; + u32 cm_l3init_fsusb_clkctrl; + u32 cm_l3init_ocp2scp1_clkctrl; + + /* cm2.l4per */ + u32 cm_l4per_clkstctrl; + u32 cm_l4per_dynamicdep; + u32 cm_l4per_adc_clkctrl; + u32 cm_l4per_gptimer10_clkctrl; + u32 cm_l4per_gptimer11_clkctrl; + u32 cm_l4per_gptimer2_clkctrl; + u32 cm_l4per_gptimer3_clkctrl; + u32 cm_l4per_gptimer4_clkctrl; + u32 cm_l4per_gptimer9_clkctrl; + u32 cm_l4per_elm_clkctrl; + u32 cm_l4per_gpio2_clkctrl; + u32 cm_l4per_gpio3_clkctrl; + u32 cm_l4per_gpio4_clkctrl; + u32 cm_l4per_gpio5_clkctrl; + u32 cm_l4per_gpio6_clkctrl; + u32 cm_l4per_hdq1w_clkctrl; + u32 cm_l4per_hecc1_clkctrl; + u32 cm_l4per_hecc2_clkctrl; + u32 cm_l4per_i2c1_clkctrl; + u32 cm_l4per_i2c2_clkctrl; + u32 cm_l4per_i2c3_clkctrl; + u32 cm_l4per_i2c4_clkctrl; + u32 cm_l4per_l4per_clkctrl; + u32 cm_l4per_mcasp2_clkctrl; + u32 cm_l4per_mcasp3_clkctrl; + u32 cm_l4per_mgate_clkctrl; + u32 cm_l4per_mcspi1_clkctrl; + u32 cm_l4per_mcspi2_clkctrl; + u32 cm_l4per_mcspi3_clkctrl; + u32 cm_l4per_mcspi4_clkctrl; + u32 cm_l4per_gpio7_clkctrl; + u32 cm_l4per_gpio8_clkctrl; + u32 cm_l4per_mmcsd3_clkctrl; + u32 cm_l4per_mmcsd4_clkctrl; + u32 cm_l4per_msprohg_clkctrl; + u32 cm_l4per_slimbus2_clkctrl; + u32 cm_l4per_uart1_clkctrl; + u32 cm_l4per_uart2_clkctrl; + u32 cm_l4per_uart3_clkctrl; + u32 cm_l4per_uart4_clkctrl; + u32 cm_l4per_mmcsd5_clkctrl; + u32 cm_l4per_i2c5_clkctrl; + u32 cm_l4per_uart5_clkctrl; + u32 cm_l4per_uart6_clkctrl; + u32 cm_l4sec_clkstctrl; + u32 cm_l4sec_staticdep; + u32 cm_l4sec_dynamicdep; + u32 cm_l4sec_aes1_clkctrl; + u32 cm_l4sec_aes2_clkctrl; + u32 cm_l4sec_des3des_clkctrl; + u32 cm_l4sec_pkaeip29_clkctrl; + u32 cm_l4sec_rng_clkctrl; + u32 cm_l4sec_sha2md51_clkctrl; + u32 cm_l4sec_cryptodma_clkctrl; + + /* l4 wkup regs */ + u32 cm_abe_pll_ref_clksel; + u32 cm_sys_clksel; + u32 cm_wkup_clkstctrl; + u32 cm_wkup_l4wkup_clkctrl; + u32 cm_wkup_wdtimer1_clkctrl; + u32 cm_wkup_wdtimer2_clkctrl; + u32 cm_wkup_gpio1_clkctrl; + u32 cm_wkup_gptimer1_clkctrl; + u32 cm_wkup_gptimer12_clkctrl; + u32 cm_wkup_synctimer_clkctrl; + u32 cm_wkup_usim_clkctrl; + u32 cm_wkup_sarram_clkctrl; + u32 cm_wkup_keyboard_clkctrl; + u32 cm_wkup_rtc_clkctrl; + u32 cm_wkup_bandgap_clkctrl; + u32 cm_wkupaon_scrm_clkctrl; + u32 prm_vc_val_bypass; + u32 prm_vc_cfg_i2c_mode; + u32 prm_vc_cfg_i2c_clk; + u32 prm_sldo_core_setup; + u32 prm_sldo_core_ctrl; + u32 prm_sldo_mpu_setup; + u32 prm_sldo_mpu_ctrl; + u32 prm_sldo_mm_setup; + u32 prm_sldo_mm_ctrl; + + u32 cm_div_m4_dpll_core; + u32 cm_div_m5_dpll_core; + u32 cm_div_m6_dpll_core; + u32 cm_div_m7_dpll_core; + u32 cm_div_m4_dpll_iva; + u32 cm_div_m5_dpll_iva; + u32 cm_div_m4_dpll_ddrphy; + u32 cm_div_m5_dpll_ddrphy; + u32 cm_div_m6_dpll_ddrphy; + u32 cm_div_m4_dpll_per; + u32 cm_div_m5_dpll_per; + u32 cm_div_m6_dpll_per; + u32 cm_div_m7_dpll_per; + u32 cm_l3instr_intrconn_wp1_clkct; + u32 cm_l3init_usbphy_clkctrl; + u32 cm_l4per_mcbsp4_clkctrl; + u32 prm_vc_cfg_channel; +}; + +extern struct prcm_regs const **prcm; +extern struct prcm_regs const omap5_es1_prcm; +extern struct prcm_regs const omap4_prcm; + +void hw_data_init(void); /* Max value for DPLL multiplier M */ #define OMAP_DPLL_MAX_N 127 -- cgit v1.2.3 From ee9447bfe37a646a8dce182e6f625f27c10512a0 Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Mon, 4 Feb 2013 04:22:01 +0000 Subject: ARM: OMAP4+: Cleanup the clocks layer Currently there is quite a lot of code which is duplicated in the clocks code for OMAP 4 and 5 Socs. Avoiding this here by moving the clocks data to a SOC specific place and the sharing the common code. This helps in addition of a new Soc with minimal changes. Signed-off-by: R Sricharan Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini --- arch/arm/include/asm/omap_common.h | 63 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) (limited to 'arch/arm/include/asm/omap_common.h') diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index fcf9ce50d62..c2d8388b32c 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -27,6 +27,8 @@ #include +#define NUM_SYS_CLKS 7 + struct prcm_regs { /* cm1.ckgen */ u32 cm_clksel_core; @@ -324,11 +326,72 @@ struct prcm_regs { u32 prm_vc_cfg_channel; }; +struct dpll_params { + u32 m; + u32 n; + s8 m2; + s8 m3; + s8 m4_h11; + s8 m5_h12; + s8 m6_h13; + s8 m7_h14; + s8 h22; + s8 h23; +}; + +struct dpll_regs { + u32 cm_clkmode_dpll; + u32 cm_idlest_dpll; + u32 cm_autoidle_dpll; + u32 cm_clksel_dpll; + u32 cm_div_m2_dpll; + u32 cm_div_m3_dpll; + u32 cm_div_m4_h11_dpll; + u32 cm_div_m5_h12_dpll; + u32 cm_div_m6_h13_dpll; + u32 cm_div_m7_h14_dpll; + u32 reserved[3]; + u32 cm_div_h22_dpll; + u32 cm_div_h23_dpll; +}; + +struct dplls { + const struct dpll_params *mpu; + const struct dpll_params *core; + const struct dpll_params *per; + const struct dpll_params *abe; + const struct dpll_params *iva; + const struct dpll_params *usb; +}; + extern struct prcm_regs const **prcm; extern struct prcm_regs const omap5_es1_prcm; extern struct prcm_regs const omap4_prcm; +extern struct dplls const **dplls_data; +extern const u32 sys_clk_array[8]; void hw_data_init(void); + +const struct dpll_params *get_mpu_dpll_params(struct dplls const *); +const struct dpll_params *get_core_dpll_params(struct dplls const *); +const struct dpll_params *get_per_dpll_params(struct dplls const *); +const struct dpll_params *get_iva_dpll_params(struct dplls const *); +const struct dpll_params *get_usb_dpll_params(struct dplls const *); +const struct dpll_params *get_abe_dpll_params(struct dplls const *); + +void do_enable_clocks(u32 const *clk_domains, + u32 const *clk_modules_hw_auto, + u32 const *clk_modules_explicit_en, + u8 wait_for_enable); + +void setup_post_dividers(u32 const base, + const struct dpll_params *params); +u32 omap_ddr_clk(void); +u32 get_sys_clk_index(void); +void enable_basic_clocks(void); +void enable_basic_uboot_clocks(void); +void enable_non_essential_clocks(void); + /* Max value for DPLL multiplier M */ #define OMAP_DPLL_MAX_N 127 -- cgit v1.2.3 From 3fcdd4a5f8ba0e0fac4b2afdb5e90efac9f7f301 Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Mon, 4 Feb 2013 04:22:02 +0000 Subject: ARM: OMAP4+: Clean up the pmic code The pmic code is duplicated for OMAP 4 and 5. Instead move the data to Soc specific place and share the code. Signed-off-by: R Sricharan Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini --- arch/arm/include/asm/omap_common.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm/include/asm/omap_common.h') diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index c2d8388b32c..eee6893d643 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -364,10 +364,31 @@ struct dplls { const struct dpll_params *usb; }; +struct pmic_data { + u32 base_offset; + u32 step; + u32 start_code; + unsigned gpio; + int gpio_en; +}; + +struct volts { + u32 value; + u32 addr; + struct pmic_data *pmic; +}; + +struct vcores_data { + struct volts mpu; + struct volts core; + struct volts mm; +}; + extern struct prcm_regs const **prcm; extern struct prcm_regs const omap5_es1_prcm; extern struct prcm_regs const omap4_prcm; extern struct dplls const **dplls_data; +extern struct vcores_data const **omap_vcores; extern const u32 sys_clk_array[8]; void hw_data_init(void); @@ -391,6 +412,9 @@ u32 get_sys_clk_index(void); void enable_basic_clocks(void); void enable_basic_uboot_clocks(void); void enable_non_essential_clocks(void); +void scale_vcores(struct vcores_data const *); +u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic); +void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic); /* Max value for DPLL multiplier M */ #define OMAP_DPLL_MAX_N 127 -- cgit v1.2.3 From c43c8339fedc86c6c23990eaabff6feaf6742e7b Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Mon, 4 Feb 2013 04:22:04 +0000 Subject: ARM: OMAP4+: Make control module register structure generic A seperate omap_sys_ctrl_regs structure is defined for omap4 & 5. If there is any change in control module for any of the ES versions, a new structure needs to be created. In order to remove this dependency, making the register structure generic for all the omap4+ boards. Signed-off-by: R Sricharan Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini --- arch/arm/include/asm/omap_common.h | 91 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) (limited to 'arch/arm/include/asm/omap_common.h') diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index eee6893d643..2115687ad71 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -326,6 +326,94 @@ struct prcm_regs { u32 prm_vc_cfg_channel; }; +struct omap_sys_ctrl_regs { + u32 control_status; + u32 control_id_code; + u32 control_std_fuse_opp_bgap; + u32 control_ldosram_iva_voltage_ctrl; + u32 control_ldosram_mpu_voltage_ctrl; + u32 control_ldosram_core_voltage_ctrl; + u32 control_paconf_global; + u32 control_paconf_mode; + u32 control_smart1io_padconf_0; + u32 control_smart1io_padconf_1; + u32 control_smart1io_padconf_2; + u32 control_smart2io_padconf_0; + u32 control_smart2io_padconf_1; + u32 control_smart2io_padconf_2; + u32 control_smart3io_padconf_0; + u32 control_smart3io_padconf_1; + u32 control_pbias; + u32 control_i2c_0; + u32 control_camera_rx; + u32 control_hdmi_tx_phy; + u32 control_uniportm; + u32 control_dsiphy; + u32 control_mcbsplp; + u32 control_usb2phycore; + u32 control_hdmi_1; + u32 control_hsi; + u32 control_ddr3ch1_0; + u32 control_ddr3ch2_0; + u32 control_ddrch1_0; + u32 control_ddrch1_1; + u32 control_ddrch2_0; + u32 control_ddrch2_1; + u32 control_lpddr2ch1_0; + u32 control_lpddr2ch1_1; + u32 control_ddrio_0; + u32 control_ddrio_1; + u32 control_ddrio_2; + u32 control_lpddr2io1_0; + u32 control_lpddr2io1_1; + u32 control_lpddr2io1_2; + u32 control_lpddr2io1_3; + u32 control_lpddr2io2_0; + u32 control_lpddr2io2_1; + u32 control_lpddr2io2_2; + u32 control_lpddr2io2_3; + u32 control_hyst_1; + u32 control_usbb_hsic_control; + u32 control_c2c; + u32 control_core_control_spare_rw; + u32 control_core_control_spare_r; + u32 control_core_control_spare_r_c0; + u32 control_srcomp_north_side; + u32 control_srcomp_south_side; + u32 control_srcomp_east_side; + u32 control_srcomp_west_side; + u32 control_srcomp_code_latch; + u32 control_pbiaslite; + u32 control_port_emif1_sdram_config; + u32 control_port_emif1_lpddr2_nvm_config; + u32 control_port_emif2_sdram_config; + u32 control_emif1_sdram_config_ext; + u32 control_emif2_sdram_config_ext; + u32 control_smart1nopmio_padconf_0; + u32 control_smart1nopmio_padconf_1; + u32 control_padconf_mode; + u32 control_xtal_oscillator; + u32 control_i2c_2; + u32 control_ckobuffer; + u32 control_wkup_control_spare_rw; + u32 control_wkup_control_spare_r; + u32 control_wkup_control_spare_r_c0; + u32 control_srcomp_east_side_wkup; + u32 control_efuse_1; + u32 control_efuse_2; + u32 control_efuse_3; + u32 control_efuse_4; + u32 control_efuse_5; + u32 control_efuse_6; + u32 control_efuse_7; + u32 control_efuse_8; + u32 control_efuse_9; + u32 control_efuse_10; + u32 control_efuse_11; + u32 control_efuse_12; + u32 control_efuse_13; +}; + struct dpll_params { u32 m; u32 n; @@ -390,6 +478,9 @@ extern struct prcm_regs const omap4_prcm; extern struct dplls const **dplls_data; extern struct vcores_data const **omap_vcores; extern const u32 sys_clk_array[8]; +extern struct omap_sys_ctrl_regs const **ctrl; +extern struct omap_sys_ctrl_regs const omap4_ctrl; +extern struct omap_sys_ctrl_regs const omap5_ctrl; void hw_data_init(void); -- cgit v1.2.3 From eed7c0f727cf8255b193dfefd21d66dfd6dbae94 Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Tue, 12 Feb 2013 01:33:41 +0000 Subject: ARM: OMAP5: Add silicon id support for ES2.0 revision. Adding the CPU detection suport for OMAP5430 and OMAP5432 ES2.0 SOCs. Signed-off-by: R Sricharan Cc: Tom Rini Cc: Nishanth Menon --- arch/arm/include/asm/omap_common.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/include/asm/omap_common.h') diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 2115687ad71..459916785ab 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -542,4 +542,6 @@ static inline u32 omap_revision(void) #define OMAP5430_SILICON_ID_INVALID 0 #define OMAP5430_ES1_0 0x54300100 #define OMAP5432_ES1_0 0x54320100 +#define OMAP5430_ES2_0 0x54300200 +#define OMAP5432_ES2_0 0x54320200 #endif /* _OMAP_COMMON_H_ */ -- cgit v1.2.3 From afc2f9dcf1a4a478e51a84b1a162bca19c7b7715 Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Tue, 12 Feb 2013 01:33:42 +0000 Subject: ARM: OMAP5: clock: Add the prcm register changes required for ES2.0 PRCM register addresses are changed from ES1.0 to ES2.0 due to PER power domain getting moved to CORE power domain. So adding the nessecary register changes for the same. Signed-off-by: R Sricharan Reviewed-by: Tom Rini Cc: Tom Rini --- arch/arm/include/asm/omap_common.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/include/asm/omap_common.h') diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 459916785ab..08395caccf8 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -44,6 +44,8 @@ struct prcm_regs { u32 cm_div_h12_dpll_core; u32 cm_div_h13_dpll_core; u32 cm_div_h14_dpll_core; + u32 cm_div_h21_dpll_core; + u32 cm_div_h24_dpll_core; u32 cm_ssc_deltamstep_dpll_core; u32 cm_ssc_modfreqdiv_dpll_core; u32 cm_emu_override_dpll_core; @@ -128,6 +130,7 @@ struct prcm_regs { u32 cm_div_m3_dpll_per; u32 cm_div_h11_dpll_per; u32 cm_div_h12_dpll_per; + u32 cm_div_h13_dpll_per; u32 cm_div_h14_dpll_per; u32 cm_ssc_deltamstep_dpll_per; u32 cm_ssc_modfreqdiv_dpll_per; @@ -474,6 +477,7 @@ struct vcores_data { extern struct prcm_regs const **prcm; extern struct prcm_regs const omap5_es1_prcm; +extern struct prcm_regs const omap5_es2_prcm; extern struct prcm_regs const omap4_prcm; extern struct dplls const **dplls_data; extern struct vcores_data const **omap_vcores; -- cgit v1.2.3 From 47abc3df701d8bc26f311350aa523fc1d0f8ad4e Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Tue, 12 Feb 2013 01:33:43 +0000 Subject: ARM: OMAP4/5: clocks: Add the required OPP settings as per the latest addendum Change OPP settings as per the latest 0.5 version of addendum for OMAP5430 ES2.0. omap4/hw_data.c is touched here to add dummy dividers. While here correcting OPP_NOM mpu, core frequency for OMAP4430 ES2.x Note that OMAP5430 ES1.0 support is still kept alive and would be removed in a cleanup later. Signed-off-by: Lokesh Vutla Signed-off-by: R Sricharan Cc: Tom Rini Cc: Nishanth Menon --- arch/arm/include/asm/omap_common.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm/include/asm/omap_common.h') diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 08395caccf8..8a886ec9383 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -426,8 +426,10 @@ struct dpll_params { s8 m5_h12; s8 m6_h13; s8 m7_h14; + s8 h21; s8 h22; s8 h23; + s8 h24; }; struct dpll_regs { @@ -441,9 +443,11 @@ struct dpll_regs { u32 cm_div_m5_h12_dpll; u32 cm_div_m6_h13_dpll; u32 cm_div_m7_h14_dpll; - u32 reserved[3]; + u32 reserved[2]; + u32 cm_div_h21_dpll; u32 cm_div_h22_dpll; u32 cm_div_h23_dpll; + u32 cm_div_h24_dpll; }; struct dplls { -- cgit v1.2.3 From d4d986ee27fe6a78e50d4789d5b08b87a5e64892 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 12 Feb 2013 01:33:45 +0000 Subject: ARM: OMAP5: srcomp: enable slew rate compensation cells after powerup After power-up SRCOMP cells are by-passed by default in OMAP5. Software has to enable these SRCOMP sells. For ES2: All 5 SRCOMP cells needs to be enabled. For ES1: Only 4 SRCOMP cells in core power domain are enabled. The 1 in wkup domain is not enabled because smart i/os of wkup domain work with default compensation code. Signed-off-by: R Sricharan Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini Cc: Tom Rini --- arch/arm/include/asm/omap_common.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/include/asm/omap_common.h') diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 8a886ec9383..0af0c3376c4 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -153,6 +153,7 @@ struct prcm_regs { /* cm2.core */ u32 cm_coreaon_bandgap_clkctrl; + u32 cm_coreaon_io_srcomp_clkctrl; u32 cm_l3_1_clkstctrl; u32 cm_l3_1_dynamicdep; u32 cm_l3_1_l3_1_clkctrl; @@ -300,6 +301,7 @@ struct prcm_regs { u32 cm_wkup_rtc_clkctrl; u32 cm_wkup_bandgap_clkctrl; u32 cm_wkupaon_scrm_clkctrl; + u32 cm_wkupaon_io_srcomp_clkctrl; u32 prm_vc_val_bypass; u32 prm_vc_cfg_i2c_mode; u32 prm_vc_cfg_i2c_clk; -- cgit v1.2.3 From d4e4129c31cf571824a1b34aa0b9210c876be718 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Sun, 17 Feb 2013 23:33:37 +0000 Subject: arm: dra7xx: clock: Add the prcm changes PRCM register addresses are changed from OMAP5 ES2.0 to DRA7XX. So adding the necessary register changes for DRA7XX socs. Signed-off-by: Lokesh Vutla Signed-off-by: R Sricharan --- arch/arm/include/asm/omap_common.h | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) (limited to 'arch/arm/include/asm/omap_common.h') diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 0af0c3376c4..54700f7686b 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -85,6 +85,7 @@ struct prcm_regs { u32 cm_div_h12_dpll_ddrphy; u32 cm_div_h13_dpll_ddrphy; u32 cm_ssc_deltamstep_dpll_ddrphy; + u32 cm_clkmode_dpll_dsp; u32 cm_shadow_freq_config1; u32 cm_mpu_mpu_clkctrl; @@ -143,6 +144,11 @@ struct prcm_regs { u32 cm_ssc_deltamstep_dpll_usb; u32 cm_ssc_modfreqdiv_dpll_usb; u32 cm_clkdcoldo_dpll_usb; + u32 cm_clkmode_dpll_pcie_ref; + u32 cm_clkmode_apll_pcie; + u32 cm_idlest_apll_pcie; + u32 cm_div_m2_apll_pcie; + u32 cm_clkvcoldo_apll_pcie; u32 cm_clkmode_dpll_unipro; u32 cm_idlest_dpll_unipro; u32 cm_autoidle_dpll_unipro; @@ -160,7 +166,7 @@ struct prcm_regs { u32 cm_l3_2_clkstctrl; u32 cm_l3_2_dynamicdep; u32 cm_l3_2_l3_2_clkctrl; - u32 cm_l3_2_gpmc_clkctrl; + u32 cm_l3_gpmc_clkctrl; u32 cm_l3_2_ocmc_ram_clkctrl; u32 cm_mpu_m3_clkstctrl; u32 cm_mpu_m3_staticdep; @@ -205,6 +211,12 @@ struct prcm_regs { u32 cm_cam_clkstctrl; u32 cm_cam_iss_clkctrl; u32 cm_cam_fdif_clkctrl; + u32 cm_cam_vip1_clkctrl; + u32 cm_cam_vip2_clkctrl; + u32 cm_cam_vip3_clkctrl; + u32 cm_cam_lvdsrx_clkctrl; + u32 cm_cam_csi1_clkctrl; + u32 cm_cam_csi2_clkctrl; /* cm2.dss */ u32 cm_dss_clkstctrl; @@ -302,6 +314,8 @@ struct prcm_regs { u32 cm_wkup_bandgap_clkctrl; u32 cm_wkupaon_scrm_clkctrl; u32 cm_wkupaon_io_srcomp_clkctrl; + u32 prm_rstctrl; + u32 prm_rstst; u32 prm_vc_val_bypass; u32 prm_vc_cfg_i2c_mode; u32 prm_vc_cfg_i2c_clk; @@ -485,6 +499,7 @@ extern struct prcm_regs const **prcm; extern struct prcm_regs const omap5_es1_prcm; extern struct prcm_regs const omap5_es2_prcm; extern struct prcm_regs const omap4_prcm; +extern struct prcm_regs const dra7xx_prcm; extern struct dplls const **dplls_data; extern struct vcores_data const **omap_vcores; extern const u32 sys_clk_array[8]; -- cgit v1.2.3 From ea8eff1fe080bef7c5cdfea734d8ac4cdd957c4c Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 12 Feb 2013 21:29:05 +0000 Subject: arm: dra7xx: clock: Add the dplls data A new DPLL DDR is added in DRA7XX socs. Now clocks to EMIF CD is from DPLL DDR. So DPLL DDR should be locked before initializing RAM. Also adding other dpll data which are different from OMAP5 ES2.0. SYS_CLK running at 20MHz is introduced in DRA7xx socs. Signed-off-by: Lokesh Vutla Signed-off-by: R Sricharan Reviewed-by: Tom Rini --- arch/arm/include/asm/omap_common.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/include/asm/omap_common.h') diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 54700f7686b..59bfabcf314 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -27,7 +27,7 @@ #include -#define NUM_SYS_CLKS 7 +#define NUM_SYS_CLKS 8 struct prcm_regs { /* cm1.ckgen */ @@ -473,6 +473,7 @@ struct dplls { const struct dpll_params *abe; const struct dpll_params *iva; const struct dpll_params *usb; + const struct dpll_params *ddr; }; struct pmic_data { -- cgit v1.2.3 From 8b12f1779e339e375151883b3d0aadbd4fdce894 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 12 Feb 2013 21:29:06 +0000 Subject: arm: dra7xx: Add control module changes Control module register addresses are changed from OMAP5 to DRA7XX socs. So adding the necessary changes for the same. Signed-off-by: Lokesh Vutla Signed-off-by: R Sricharan Reviewed-by: Tom Rini --- arch/arm/include/asm/omap_common.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/include/asm/omap_common.h') diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 59bfabcf314..eeed1631189 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -347,11 +347,19 @@ struct prcm_regs { struct omap_sys_ctrl_regs { u32 control_status; + u32 control_core_mmr_lock1; + u32 control_core_mmr_lock2; + u32 control_core_mmr_lock3; + u32 control_core_mmr_lock4; + u32 control_core_mmr_lock5; + u32 control_core_control_io1; + u32 control_core_control_io2; u32 control_id_code; u32 control_std_fuse_opp_bgap; u32 control_ldosram_iva_voltage_ctrl; u32 control_ldosram_mpu_voltage_ctrl; u32 control_ldosram_core_voltage_ctrl; + u32 control_padconf_core_base; u32 control_paconf_global; u32 control_paconf_mode; u32 control_smart1io_padconf_0; @@ -431,6 +439,7 @@ struct omap_sys_ctrl_regs { u32 control_efuse_11; u32 control_efuse_12; u32 control_efuse_13; + u32 control_padconf_wkup_base; }; struct dpll_params { @@ -507,6 +516,7 @@ extern const u32 sys_clk_array[8]; extern struct omap_sys_ctrl_regs const **ctrl; extern struct omap_sys_ctrl_regs const omap4_ctrl; extern struct omap_sys_ctrl_regs const omap5_ctrl; +extern struct omap_sys_ctrl_regs const dra7xx_ctrl; void hw_data_init(void); -- cgit v1.2.3 From de62688bb61c499ecc2d70a3aa8ccf90bb7a8ef6 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 12 Feb 2013 21:29:03 +0000 Subject: arm: dra7xx: Add silicon id support for DRA752 soc Adding CPU detection support for the DRA752 ES1.0 soc. Signed-off-by: Lokesh Vutla Signed-off-by: R Sricharan Reviewed-by: Tom Rini --- arch/arm/include/asm/omap_common.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/include/asm/omap_common.h') diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index eeed1631189..091ddb508d5 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -580,4 +580,7 @@ static inline u32 omap_revision(void) #define OMAP5432_ES1_0 0x54320100 #define OMAP5430_ES2_0 0x54300200 #define OMAP5432_ES2_0 0x54320200 + +/* DRA7XX */ +#define DRA752_ES1_0 0x07520100 #endif /* _OMAP_COMMON_H_ */ -- cgit v1.2.3