From 8cf223133c11c8064b4c8c258403371bc1873804 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 10 Jan 2018 13:20:32 +0800 Subject: imx: cleanup bootaux Move i.MX6/7 bootaux code to imx_bootaux.c. The i.MX6/7 has different src layout, so define M4 reg offset to ease the cleanup. Redefine the M4 related BIT for share common code. Signed-off-by: Peng Fan Cc: Stefano Babic Cc: Fabio Estevam --- arch/arm/mach-imx/imx_bootaux.c | 36 ++++++++++++++++++++++++++++-------- 1 file changed, 28 insertions(+), 8 deletions(-) (limited to 'arch/arm/mach-imx/imx_bootaux.c') diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index b62dfbf6bf6..02728514b78 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -5,21 +5,41 @@ */ #include +#include #include #include -/* Allow for arch specific config before we boot */ -int __weak arch_auxiliary_core_up(u32 core_id, u32 boot_private_data) +int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) { - /* please define platform specific arch_auxiliary_core_up() */ - return CMD_RET_FAILURE; + ulong stack, pc; + + if (!boot_private_data) + return -EINVAL; + + stack = *(ulong *)boot_private_data; + pc = *(ulong *)(boot_private_data + 4); + + /* Set the stack and pc to M4 bootROM */ + writel(stack, M4_BOOTROM_BASE_ADDR); + writel(pc, M4_BOOTROM_BASE_ADDR + 4); + + /* Enable M4 */ + clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET, + SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK); + + return 0; } -/* Allow for arch specific config before we boot */ -int __weak arch_auxiliary_core_check_up(u32 core_id) +int arch_auxiliary_core_check_up(u32 core_id) { - /* please define platform specific arch_auxiliary_core_check_up() */ - return 0; + unsigned int val; + + val = readl(SRC_BASE_ADDR + SRC_M4_REG_OFFSET); + + if (val & SRC_M4C_NON_SCLR_RST_MASK) + return 0; /* assert in reset */ + + return 1; } /* -- cgit v1.2.3 From ecd7ab56284613a92975a9ea5063015cb2a6ce43 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 10 Jan 2018 13:20:33 +0800 Subject: imx: bootaux: support i.MX8M Add i.MX8M support. Because i.MX8M use SiP call trap to Arm Trusted Firmware to handle M4, so use #ifdef to avoid build error on i.MX6/7. Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx_bootaux.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/mach-imx/imx_bootaux.c') diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index 02728514b78..6256b3a778f 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -6,7 +6,9 @@ #include #include +#include #include +#include #include int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) @@ -24,14 +26,21 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) writel(pc, M4_BOOTROM_BASE_ADDR + 4); /* Enable M4 */ +#ifdef CONFIG_MX8M + call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0); +#else clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET, SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK); +#endif return 0; } int arch_auxiliary_core_check_up(u32 core_id) { +#ifdef CONFIG_MX8M + return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0); +#else unsigned int val; val = readl(SRC_BASE_ADDR + SRC_M4_REG_OFFSET); @@ -40,6 +49,7 @@ int arch_auxiliary_core_check_up(u32 core_id) return 0; /* assert in reset */ return 1; +#endif } /* -- cgit v1.2.3