From 508791a035ea8e2698c52e1547f77048c49c4391 Mon Sep 17 00:00:00 2001 From: Ley Foon Tan Date: Fri, 18 May 2018 22:05:22 +0800 Subject: arm: socfpga: stratix10: Add clock manager driver for Stratix10 SoC Add Clock Manager driver support for Stratix SoC Signed-off-by: Chin Liang See Signed-off-by: Ley Foon Tan --- arch/arm/mach-socfpga/clock_manager.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-socfpga/clock_manager.c') diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index bc2c0f8854a..59ede59b599 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -20,7 +20,7 @@ void cm_wait_for_lock(u32 mask) do { #if defined(CONFIG_TARGET_SOCFPGA_GEN5) inter_val = readl(&clock_manager_base->inter) & mask; -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#else inter_val = readl(&clock_manager_base->stat) & mask; #endif /* Wait for stable lock */ @@ -51,7 +51,7 @@ int set_cpu_clk_info(void) #if defined(CONFIG_TARGET_SOCFPGA_GEN5) gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000; -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#else gd->bd->bi_ddr_freq = 0; #endif -- cgit v1.2.3