From 35638172f99a4974489a8ea85f4727382bcde22d Mon Sep 17 00:00:00 2001 From: Tien Fong Chee Date: Wed, 18 Sep 2024 16:43:02 +0800 Subject: arm: socfpga: agilex5: Add new driver model for system manager in Agilex5 Initial creation of new system manager driver. Add supports for the SOCFPGA System Manager Register block which aggregates different peripheral function into one area. On 64 bit ARM parts, the system manager only can be accessed during EL3 mode, this driver model provide user the high level access to system register and abstract user from low level access. The base address of system manager can be retrieved using DT framework through the System Manager driver. Signed-off-by: Tien Fong Chee Signed-off-by: Boon Khai Ng --- arch/arm/mach-socfpga/misc.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) (limited to 'arch/arm/mach-socfpga/misc.c') diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 46f9c82bbb2..9d464307665 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -248,10 +248,6 @@ void socfpga_get_managers_addr(void) if (ret) hang(); - ret = socfpga_get_base_addr("altr,sys-mgr", &socfpga_sysmgr_base); - if (ret) - hang(); - #ifdef CONFIG_TARGET_SOCFPGA_AGILEX ret = socfpga_get_base_addr("intel,agilex-clkmgr", &socfpga_clkmgr_base); @@ -265,6 +261,20 @@ void socfpga_get_managers_addr(void) hang(); } +void socfpga_get_sys_mgr_addr(const char *compat) +{ + int ret; + struct udevice *sysmgr_dev; + + ret = uclass_get_device_by_name(UCLASS_NOP, compat, &sysmgr_dev); + if (ret) { + printf("Altera system manager init failed: %d\n", ret); + hang(); + } else { + socfpga_sysmgr_base = (phys_addr_t)dev_read_addr(sysmgr_dev); + } +} + phys_addr_t socfpga_get_rstmgr_addr(void) { return socfpga_rstmgr_base; -- cgit v1.2.3 From 6d07e1980c96886c54ba67c7eef589b387794e1d Mon Sep 17 00:00:00 2001 From: Alif Zakuan Yuslaimi Date: Tue, 18 Feb 2025 16:34:47 +0800 Subject: arm: socfpga: misc: Exclude Agilex5 from clock manager base address retrieval Agilex5 retrieves its clock manager address via probing its own clock driver model during SPL initialization. Therefore, excluding Agilex5 from calling generic clock driver in misc driver. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee --- arch/arm/mach-socfpga/misc.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) (limited to 'arch/arm/mach-socfpga/misc.c') diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 9d464307665..fbe3af845d8 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2012-2017 Altera Corporation + * Copyright (C) 2012-2025 Altera Corporation */ #include @@ -248,15 +248,16 @@ void socfpga_get_managers_addr(void) if (ret) hang(); -#ifdef CONFIG_TARGET_SOCFPGA_AGILEX - ret = socfpga_get_base_addr("intel,agilex-clkmgr", - &socfpga_clkmgr_base); -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) - ret = socfpga_get_base_addr("intel,n5x-clkmgr", - &socfpga_clkmgr_base); -#else - ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base); -#endif + if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX)) + ret = socfpga_get_base_addr("intel,agilex-clkmgr", + &socfpga_clkmgr_base); + else if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)) + ret = socfpga_get_base_addr("intel,n5x-clkmgr", + &socfpga_clkmgr_base); + else if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) + ret = socfpga_get_base_addr("altr,clk-mgr", + &socfpga_clkmgr_base); + if (ret) hang(); } -- cgit v1.2.3 From 04ea9147d5bdab1370ced118acf35db7ac9e281c Mon Sep 17 00:00:00 2001 From: Tingting Meng Date: Fri, 21 Feb 2025 21:49:41 +0800 Subject: ddr: altera: Add DDR driver for Agilex5 series Adding DDR driver support for Agilex5 series. Signed-off-by: Tingting Meng --- arch/arm/mach-socfpga/misc.c | 36 ++++++++++++++++++++++++------------ 1 file changed, 24 insertions(+), 12 deletions(-) (limited to 'arch/arm/mach-socfpga/misc.c') diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index fbe3af845d8..97e01140513 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -5,27 +5,29 @@ #include #include -#include -#include -#include -#include -#include -#include #include +#include +#include +#include +#include #include #include -#include +#include #include #include -#include +#include +#include +#include +#include #include +#include #include #include -#include -#include #include -#include -#include +#include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -51,8 +53,18 @@ struct bsel bsel_str[] = { int dram_init(void) { +#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + struct spl_handoff *ho; + + ho = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF, sizeof(*ho)); + if (!ho) + return log_msg_ret("Missing SPL hand-off info", -ENOENT); + gd->ram_size = ho->ram_bank[0].size; + gd->ram_base = ho->ram_bank[0].start; +#else if (fdtdec_setup_mem_size_base() != 0) return -EINVAL; +#endif /* HANDOFF && CONFIG_TARGET_SOCFPGA_AGILEX5 */ return 0; } -- cgit v1.2.3