From 6ec6b75e9a9b3b4dfd55d7eac112c2f1171163de Mon Sep 17 00:00:00 2001 From: Alif Zakuan Yuslaimi Date: Tue, 18 Feb 2025 16:35:00 +0800 Subject: arm: socfpga: agilex5: Update CPU info Update the print info per Agilex5 Signed-off-by: Tien Fong Chee Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee --- arch/arm/mach-socfpga/misc_soc64.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-socfpga/misc_soc64.c') diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c index a6cc78454da..573a8f79cae 100644 --- a/arch/arm/mach-socfpga/misc_soc64.c +++ b/arch/arm/mach-socfpga/misc_soc64.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2016-2018 Intel Corporation + * Copyright (C) 2025 Altera Corporation * */ @@ -45,7 +46,8 @@ static Altera_desc altera_fpga[] = { #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { - puts("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n"); + printf("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-%s)\n", + IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) ? "A55/A76" : "A53"); return 0; } -- cgit v1.2.3 From 8c172a423cb6268eb787142b748b50473b80d88c Mon Sep 17 00:00:00 2001 From: Alif Zakuan Yuslaimi Date: Tue, 18 Feb 2025 16:35:01 +0800 Subject: arm: socfpga: Export board ID as U-Boot environment Board ID is exported as environment variable for use to boot Linux with FIT configuration. Signed-off-by: Alif Zakuan Yuslaimi Signed-off-by: Tien Fong Chee Reviewed-by: Tien Fong Chee --- arch/arm/mach-socfpga/misc_soc64.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/mach-socfpga/misc_soc64.c') diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c index 573a8f79cae..793b8b8e390 100644 --- a/arch/arm/mach-socfpga/misc_soc64.c +++ b/arch/arm/mach-socfpga/misc_soc64.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -57,10 +58,15 @@ int print_cpuinfo(void) int arch_misc_init(void) { char qspi_string[13]; + unsigned long id; sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz()); env_set("qspi_clock", qspi_string); + /* Export board_id as environment variable */ + id = socfpga_get_board_id(); + env_set_ulong("board_id", id); + return 0; } #endif -- cgit v1.2.3 From 04ea9147d5bdab1370ced118acf35db7ac9e281c Mon Sep 17 00:00:00 2001 From: Tingting Meng Date: Fri, 21 Feb 2025 21:49:41 +0800 Subject: ddr: altera: Add DDR driver for Agilex5 series Adding DDR driver support for Agilex5 series. Signed-off-by: Tingting Meng --- arch/arm/mach-socfpga/misc_soc64.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) (limited to 'arch/arm/mach-socfpga/misc_soc64.c') diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c index 793b8b8e390..e0b2b4237e1 100644 --- a/arch/arm/mach-socfpga/misc_soc64.c +++ b/arch/arm/mach-socfpga/misc_soc64.c @@ -6,17 +6,18 @@ */ #include +#include +#include +#include +#include #include #include #include #include #include #include +#include #include -#include -#include -#include -#include #include DECLARE_GLOBAL_DATA_PTR; @@ -41,6 +42,19 @@ static Altera_desc altera_fpga[] = { }, }; +/* + * The Agilex5 platform has enabled the bloblist feature, and the bloblist + * address and size are initialized based on the defconfig settings. + * During the SPL phase, this function is used to prevent the bloblist + * from initializing its address and size with the saved boot parameters, + * which may have been incorrectly set. + */ +void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, + unsigned long r3) +{ + save_boot_params_ret(); +} + /* * Print CPU information */ -- cgit v1.2.3