From de7781158923a9c87debc5a89ce4fabfd0fc93bc Mon Sep 17 00:00:00 2001 From: Ley Foon Tan Date: Wed, 26 Apr 2017 02:44:33 +0800 Subject: arm: socfpga: Restructure clock manager driver Restructure clock manager driver in the preparation to support A10. Move the Gen5 specific code to _gen5 files. - Change all uint32_t to u32 and change to use macro BIT(n) for bit shift. - Check return value from wait_for_bit(). So change return type to int for cm_write_with_phase() and cm_basic_init(). Signed-off-by: Ley Foon Tan --- arch/arm/mach-socfpga/spl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-socfpga/spl.c') diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c index fec4c7a9910..0064fc8a9d5 100644 --- a/arch/arm/mach-socfpga/spl.c +++ b/arch/arm/mach-socfpga/spl.c @@ -127,7 +127,8 @@ void board_init_f(ulong dummy) debug("Reconfigure Clock Manager\n"); /* reconfigure the PLLs */ - cm_basic_init(cm_default_cfg); + if (cm_basic_init(cm_default_cfg)) + hang(); /* Enable bootrom to configure IOs. */ sysmgr_config_warmrstcfgio(1); -- cgit v1.2.3 From 8f4c80c4fd02c6b35bdd48118d1af5ba2dc2c38d Mon Sep 17 00:00:00 2001 From: Ley Foon Tan Date: Wed, 26 Apr 2017 02:44:45 +0800 Subject: arm: socfpga: Add SPL support for Arria 10 Add SPL support for Arria 10. Signed-off-by: Tien Fong Chee Signed-off-by: Ley Foon Tan --- arch/arm/mach-socfpga/spl.c | 53 +++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 51 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-socfpga/spl.c') diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c index 0064fc8a9d5..71bae827a15 100644 --- a/arch/arm/mach-socfpga/spl.c +++ b/arch/arm/mach-socfpga/spl.c @@ -19,23 +19,32 @@ #include #include #include +#include +#include +#include +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#include +#endif DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; static struct scu_registers *scu_regs = (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; -static struct socfpga_system_manager *sysmgr_regs = +#endif + +static const struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; u32 spl_boot_device(void) { const u32 bsel = readl(&sysmgr_regs->bootinfo); - switch (bsel & 0x7) { + switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) { case 0x1: /* FPGA (HPS2FPGA Bridge) */ return BOOT_DEVICE_RAM; case 0x2: /* NAND Flash (1.8V) */ @@ -68,6 +77,7 @@ u32 spl_boot_mode(const u32 boot_device) } #endif +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static void socfpga_nic301_slave_ns(void) { writel(0x1, &nic301_regs->lwhps2fpgaregs); @@ -183,3 +193,42 @@ void board_init_f(ulong dummy) /* Configure simple malloc base pointer into RAM. */ gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024); } +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +void spl_board_init(void) +{ + /* configuring the clock based on handoff */ + cm_basic_init(gd->fdt_blob); + WATCHDOG_RESET(); + + config_dedicated_pins(gd->fdt_blob); + WATCHDOG_RESET(); + + /* Release UART from reset */ + socfpga_reset_uart(0); + + /* enable console uart printing */ + preloader_console_init(); +} + +void board_init_f(ulong dummy) +{ + /* + * Configure Clock Manager to use intosc clock instead external osc to + * ensure success watchdog operation. We do it as early as possible. + */ + cm_use_intosc(); + + socfpga_watchdog_disable(); + + arch_early_init_r(); + +#ifdef CONFIG_HW_WATCHDOG + /* release osc1 watchdog timer 0 from reset */ + socfpga_reset_deassert_osc1wd0(); + + /* reconfigure and enable the watchdog */ + hw_watchdog_init(); + WATCHDOG_RESET(); +#endif /* CONFIG_HW_WATCHDOG */ +} +#endif -- cgit v1.2.3