From 40f5046c221a7b2719c49b51acefe12914b213e5 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 29 May 2024 16:47:58 +0200 Subject: arm64: versal2: Add support for AMD Versal Gen 2 Add support for AMD Versal Gen 2. SoC is based on Cortex-a78ae 4 cluster/2 cpu core each. A lot of IPs are shared with previous families. There are couple of new IP blocks where the most interesting from user point of view is UFS. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/bc2b70831ce1031bd0fac32357bff84936e1310f.1716994063.git.michal.simek@amd.com --- arch/arm/mach-versal2/clk.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 arch/arm/mach-versal2/clk.c (limited to 'arch/arm/mach-versal2/clk.c') diff --git a/arch/arm/mach-versal2/clk.c b/arch/arm/mach-versal2/clk.c new file mode 100644 index 00000000000..e73ae9af076 --- /dev/null +++ b/arch/arm/mach-versal2/clk.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. + * + * Michal Simek + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_CLOCKS +/** + * set_cpu_clk_info - Initialize clock framework + * + * Return: 0 always. + * + * This function is called from common code after relocation and sets up the + * clock framework. The framework must not be used before this function had been + * called. + */ +int set_cpu_clk_info(void) +{ + gd->cpu_clk = get_tbclk(); + + gd->bd->bi_arm_freq = gd->cpu_clk / 1000000; + gd->bd->bi_dsp_freq = 0; + + return 0; +} +#endif -- cgit v1.2.3