From 7048bb13b2d6309ef8386fca665247d3afa36ab0 Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Thu, 6 Feb 2020 10:45:40 +0100 Subject: mips: vcoreiii: Fix cache coherency issues This patch fixes an stability issue seen on some vcoreiii targets, which was root caused to a cache inconsistency situation. The inconsistency was caused by having kuseg pointing to NOR area but used as a stack/gd/heap area during initialization, while only relatively late remapping the RAM area into kuseg position. The fix is to initialize the DDR right after the TLB setup, and then remapping it into position before gd/stack/heap usage. Reported-by: Ramin Seyed-Moussavi Reviewed-by: Alexandre Belloni Reviewed-by: Horatiu Vultur Signed-off-by: Lars Povlsen --- arch/mips/mach-mscc/include/mach/ddr.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch/mips/mach-mscc/include/mach/ddr.h') diff --git a/arch/mips/mach-mscc/include/mach/ddr.h b/arch/mips/mach-mscc/include/mach/ddr.h index d1f4287f654..bf75e52ec3c 100644 --- a/arch/mips/mach-mscc/include/mach/ddr.h +++ b/arch/mips/mach-mscc/include/mach/ddr.h @@ -435,16 +435,12 @@ static inline void hal_vcoreiii_ddr_failed(void) reset = KSEG0ADDR(_machine_restart); icache_lock((void *)reset, 128); asm volatile ("jr %0"::"r" (reset)); - - panic("DDR init failed\n"); } #else /* JR2 || ServalT */ static inline void hal_vcoreiii_ddr_failed(void) { writel(0, BASE_CFG + ICPU_RESET); writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_CFG + PERF_SOFT_RST); - - panic("DDR init failed\n"); } #endif -- cgit v1.2.3