From 7e157b0ade85282a76db27cbf0ab8a2370d4d7b6 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Fri, 18 Oct 2013 11:47:20 +0200 Subject: mpc8xxx: set x2 DDR3 refresh rate if SPD config requires it If the DDR3 module supports industrial temperature range and requires the x2 refresh rate for that temp range, the refresh period must be 3.9us instead of 7.8 us. This was successfuly tested on kmp204x board with some MT41K128M16 DDR3 RAM chips (no module used, chips directly soldered on board with an SPD EEPROM). Signed-off-by: Valentin Longchamp [York Sun: fix minor conflicts in fsl_ddr_dimm_params.h, lc_common_dimm_params.c, common_timing_params.h] Acked-by: York Sun --- arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c') diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c index d82eb674d34..4c8645da569 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c @@ -321,6 +321,10 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, * = 3.9 us at ext temperature range */ pdimm->refresh_rate_ps = 7800000; + if ((spd->therm_ref_opt & 0x1) && !(spd->therm_ref_opt & 0x2)) { + pdimm->refresh_rate_ps = 3900000; + pdimm->extended_op_srt = 1; + } /* * min four active window delay time -- cgit v1.2.3