From 3c1bfc04c6292070ac4bd0a39976a3dbe6f00aa0 Mon Sep 17 00:00:00 2001 From: Jeffrey Ladouceur Date: Fri, 25 Jan 2013 10:38:53 +0000 Subject: powerpc/mpc85xx: Add revision properties in portal device tree node 'pme' The 'fsl,pme-rev1' and 'fsl-pme-rev2' properties have been added to the pme portal node. This is required for software to determine which version of PME hardware is present and take appropriate actions. These properties are a direct reflection of the corresponding ccsr pme register value. Also removed unnecessary static global variables. Signed-off-by: Jeffrey Ladouceur Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/portals.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) (limited to 'arch/powerpc/cpu') diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c index b59ef69f1f6..d529095ee8c 100644 --- a/arch/powerpc/cpu/mpc85xx/portals.c +++ b/arch/powerpc/cpu/mpc85xx/portals.c @@ -30,11 +30,9 @@ #include #include -static ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR; -static ccsr_bman_t *bman = (void *)CONFIG_SYS_FSL_BMAN_ADDR; - void setup_portals(void) { + ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR; #ifdef CONFIG_FSL_CORENET int i; @@ -166,6 +164,20 @@ static int fdt_qportal(void *blob, int off, int id, char *name, num = get_dpaa_liodn(dev, &liodns[0], id); ret = fdt_setprop(blob, childoff, "fsl,liodn", &liodns[0], sizeof(u32) * num); + if (!strncmp(name, "pme", 3)) { + u32 pme_rev1, pme_rev2; + ccsr_pme_t *pme_regs = + (void *)CONFIG_SYS_FSL_CORENET_PME_ADDR; + + pme_rev1 = in_be32(&pme_regs->pm_ip_rev_1); + pme_rev2 = in_be32(&pme_regs->pm_ip_rev_2); + ret = fdt_setprop(blob, childoff, + "fsl,pme-rev1", &pme_rev1, sizeof(u32)); + if (ret < 0) + return ret; + ret = fdt_setprop(blob, childoff, + "fsl,pme-rev2", &pme_rev2, sizeof(u32)); + } #endif } else { return childoff; @@ -183,6 +195,7 @@ void fdt_fixup_qportals(void *blob) int off, err; unsigned int maj, min; unsigned int ip_cfg; + ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR; u32 rev_1 = in_be32(&qman->ip_rev_1); u32 rev_2 = in_be32(&qman->ip_rev_2); char compat[64]; @@ -272,6 +285,7 @@ void fdt_fixup_bportals(void *blob) int off, err; unsigned int maj, min; unsigned int ip_cfg; + ccsr_bman_t *bman = (void *)CONFIG_SYS_FSL_BMAN_ADDR; u32 rev_1 = in_be32(&bman->ip_rev_1); u32 rev_2 = in_be32(&bman->ip_rev_2); char compat[64]; -- cgit v1.2.3 From f5c2623d80d72e397f1d6211b9691f7580461166 Mon Sep 17 00:00:00 2001 From: "Dongsheng.wang@freescale.com" Date: Wed, 30 Jan 2013 18:51:52 +0000 Subject: powerpc/mpc85xx: add setting of clock-frequency for mpic node Set the device tree property associated with the mpic source frequency. The frequency is used for mpic timer. Signed-off-by: Wang Dongsheng Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/fdt.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/powerpc/cpu') diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 24eb9789be9..6f8d09ecc46 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -663,6 +663,11 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_FSL_CORENET do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0", "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); + do_fixup_by_compat_u32(blob, "fsl,mpic", + "clock-frequency", get_bus_freq(0)/2, 1); +#else + do_fixup_by_compat_u32(blob, "fsl,mpic", + "clock-frequency", get_bus_freq(0), 1); #endif fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); -- cgit v1.2.3 From 7b700d212532b1b7b11e003d6949407d74fb69e3 Mon Sep 17 00:00:00 2001 From: Tang Yuantian Date: Thu, 28 Feb 2013 23:24:34 +0000 Subject: powerpc/mpc85xx: set clock-frequency for T4/B4 clockgen node For T4/B4, the clockgen node compatible string is updated to version 2. Add clock-frequency setting for this new version. Signed-off-by: Tang Yuantian Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/fdt.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/powerpc/cpu') diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 6f8d09ecc46..288f7b28603 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -663,6 +663,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_FSL_CORENET do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0", "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); + do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2", + "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); do_fixup_by_compat_u32(blob, "fsl,mpic", "clock-frequency", get_bus_freq(0)/2, 1); #else -- cgit v1.2.3 From 99d7b0a43ddec619739f38dc6a92777a4595182c Mon Sep 17 00:00:00 2001 From: Xulei Date: Mon, 11 Mar 2013 17:56:34 +0000 Subject: powerpc/85xx: Add workaround for errata USB-14 (enable on P204x/P3041/P50x0) On P204x/P304x/P50x0 Rev1.0, USB transmit will result in false internal multi-bit ECC errors, which has impact on performance, so software should disable all ECC reporting from USB1 and USB2. In formal release document, the errata number should be USB14 instead of USB138. Signed-off-by: xulei Signed-off-by: Roy Zang Signed-off-by: Kumar Gala Signed-off-by: xulei Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 14 ++++++++++++++ 2 files changed, 17 insertions(+) (limited to 'arch/powerpc/cpu') diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 5d72f4c342d..422782ca8f2 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -254,6 +254,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #endif #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003 puts("Work-around for Erratum PCIe-A003 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_USB14 + puts("Work-around for Erratum USB14 enabled\n"); #endif return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index de9d9161115..53713e31d42 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -623,6 +623,20 @@ skip_l2: } #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_USB14 + /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal + * multi-bit ECC errors which has impact on performance, so software + * should disable all ECC reporting from USB1 and USB2. + */ + if (IS_SVR_REV(get_svr(), 1, 0)) { + struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *) + (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET); + setbits_be32(&dcfg->ecccr1, + (DCSR_DCFG_ECC_DISABLE_USB1 | + DCSR_DCFG_ECC_DISABLE_USB2)); + } +#endif + #ifdef CONFIG_FMAN_ENET fman_enet_init(); #endif -- cgit v1.2.3 From df616cae64561ba4773a75469b425698346c4ce8 Mon Sep 17 00:00:00 2001 From: Horst Kronstorfer Date: Wed, 13 Mar 2013 10:14:05 +0000 Subject: mpc85xx: Fix a compiler warning when CONFIG_WATCHDOG is turned on cpu.c:288:2: warning: implicit declaration of function 'reset_85xx_watchdog' [-Wimplicit-function-declaration] Signed-off-by: Horst Kronstorfer Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/cpu.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) (limited to 'arch/powerpc/cpu') diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index df2ab6d73cb..6ce483e17ae 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -281,14 +281,6 @@ unsigned long get_tbclk (void) #if defined(CONFIG_WATCHDOG) -void -watchdog_reset(void) -{ - int re_enable = disable_interrupts(); - reset_85xx_watchdog(); - if (re_enable) enable_interrupts(); -} - void reset_85xx_watchdog(void) { @@ -297,6 +289,16 @@ reset_85xx_watchdog(void) */ mtspr(SPRN_TSR, TSR_WIS); } + +void +watchdog_reset(void) +{ + int re_enable = disable_interrupts(); + + reset_85xx_watchdog(); + if (re_enable) + enable_interrupts(); +} #endif /* CONFIG_WATCHDOG */ /* -- cgit v1.2.3 From ca9131c0569a98b6538c5a2d78c3d845bdf54bae Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Mon, 25 Mar 2013 07:30:08 +0000 Subject: powerpc/85xx: add SerDes bank 4 lanes Only some chips have four SerDes banks, so don't define lanes for a bank that doesn't exist. Signed-off-by: Timur Tabi Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/powerpc/cpu') diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 825a29238db..b621adf4af5 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -103,6 +103,10 @@ static const struct { { 22, 168, FSL_SRDS_BANK_3 }, { 23, 169, FSL_SRDS_BANK_3 }, #endif +#if SRDS_MAX_BANK > 3 + { 24, 175, FSL_SRDS_BANK_4 }, + { 25, 176, FSL_SRDS_BANK_4 }, +#endif }; int serdes_get_lane_idx(int lane) -- cgit v1.2.3 From 1f06c9af31a274c8fd1263045d10b5a782fe8e45 Mon Sep 17 00:00:00 2001 From: Cristian Sovaiala Date: Mon, 25 Mar 2013 07:30:12 +0000 Subject: powerpc/mpc85xx: Changed LIODN offset values Extending LIODN offset range from 1-5 to 1-10 While using a qman portal with a higher index the LIODN offset is incorrectly set, thus extending the range of offsets covers all 10 qman portals Signed-off-by: Cristian Sovaiala Acked-by: Haiying Wang Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/p2041_ids.c | 20 ++++++++++---------- arch/powerpc/cpu/mpc85xx/p3041_ids.c | 20 ++++++++++---------- arch/powerpc/cpu/mpc85xx/p5020_ids.c | 20 ++++++++++---------- 3 files changed, 30 insertions(+), 30 deletions(-) (limited to 'arch/powerpc/cpu') diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c index 91d9cac5682..ef685fea092 100644 --- a/arch/powerpc/cpu/mpc85xx/p2041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c @@ -27,16 +27,16 @@ #ifdef CONFIG_SYS_DPAA_QBMAN struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ - SET_QP_INFO(1, 2, 1, 0), - SET_QP_INFO(3, 4, 2, 1), - SET_QP_INFO(5, 6, 3, 2), - SET_QP_INFO(7, 8, 4, 3), - SET_QP_INFO(9, 10, 5, 0), - SET_QP_INFO(11, 12, 1, 1), - SET_QP_INFO(13, 14, 2, 2), - SET_QP_INFO(15, 16, 3, 3), - SET_QP_INFO(17, 18, 4, 0), /* for now sdest to 0 */ - SET_QP_INFO(19, 20, 5, 0), /* for now sdest to 0 */ + SET_QP_INFO(1, 2, 1, 0), + SET_QP_INFO(3, 4, 2, 1), + SET_QP_INFO(5, 6, 3, 2), + SET_QP_INFO(7, 8, 4, 3), + SET_QP_INFO(9, 10, 5, 0), + SET_QP_INFO(11, 12, 6, 1), + SET_QP_INFO(13, 14, 7, 2), + SET_QP_INFO(15, 16, 8, 3), + SET_QP_INFO(17, 18, 9, 0), /* for now sdest to 0 */ + SET_QP_INFO(19, 20, 10, 0), /* for now sdest to 0 */ }; #endif diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c index e46a714dccd..cab03f8ab6e 100644 --- a/arch/powerpc/cpu/mpc85xx/p3041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c @@ -27,16 +27,16 @@ #ifdef CONFIG_SYS_DPAA_QBMAN struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ - SET_QP_INFO(1, 2, 1, 0), - SET_QP_INFO(3, 4, 2, 1), - SET_QP_INFO(5, 6, 3, 2), - SET_QP_INFO(7, 8, 4, 3), - SET_QP_INFO(9, 10, 5, 0), - SET_QP_INFO(11, 12, 1, 1), - SET_QP_INFO(13, 14, 2, 2), - SET_QP_INFO(15, 16, 3, 3), - SET_QP_INFO(17, 18, 4, 0), /* for now sdest to 0 */ - SET_QP_INFO(19, 20, 5, 0), /* for now sdest to 0 */ + SET_QP_INFO(1, 2, 1, 0), + SET_QP_INFO(3, 4, 2, 1), + SET_QP_INFO(5, 6, 3, 2), + SET_QP_INFO(7, 8, 4, 3), + SET_QP_INFO(9, 10, 5, 0), + SET_QP_INFO(1, 12, 6, 1), + SET_QP_INFO(13, 14, 7, 2), + SET_QP_INFO(15, 16, 8, 3), + SET_QP_INFO(17, 18, 9, 0), /* for now sdest to 0 */ + SET_QP_INFO(19, 20, 10, 0), /* for now sdest to 0 */ }; #endif diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/arch/powerpc/cpu/mpc85xx/p5020_ids.c index e8c26bf44c8..ca05b9cb2b4 100644 --- a/arch/powerpc/cpu/mpc85xx/p5020_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5020_ids.c @@ -27,16 +27,16 @@ #ifdef CONFIG_SYS_DPAA_QBMAN struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ - SET_QP_INFO(1, 2, 1, 0), - SET_QP_INFO(3, 4, 2, 1), - SET_QP_INFO(5, 6, 3, 0), - SET_QP_INFO(7, 8, 4, 1), - SET_QP_INFO(9, 10, 5, 0), - SET_QP_INFO(11, 12, 1, 1), - SET_QP_INFO(13, 14, 2, 0), - SET_QP_INFO(15, 16, 3, 1), - SET_QP_INFO(17, 18, 4, 0), - SET_QP_INFO(19, 20, 5, 1), + SET_QP_INFO(1, 2, 1, 0), + SET_QP_INFO(3, 4, 2, 1), + SET_QP_INFO(5, 6, 3, 0), + SET_QP_INFO(7, 8, 4, 1), + SET_QP_INFO(9, 10, 5, 0), + SET_QP_INFO(11, 12, 6, 1), + SET_QP_INFO(13, 14, 7, 0), + SET_QP_INFO(15, 16, 8, 1), + SET_QP_INFO(17, 18, 9, 0), + SET_QP_INFO(19, 20, 10, 1), }; #endif -- cgit v1.2.3