From c9056653ecd6dfedc5e9f00548f9f1c604a3a193 Mon Sep 17 00:00:00 2001 From: Lukas Auer Date: Fri, 4 Jan 2019 01:37:29 +0100 Subject: riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng --- arch/riscv/lib/cache.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) (limited to 'arch/riscv/lib/cache.c') diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index ae5c60716ff..78b19da2c5d 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -11,13 +11,12 @@ void invalidate_icache_all(void) asm volatile ("fence.i" ::: "memory"); } -void flush_dcache_all(void) +__weak void flush_dcache_all(void) { - asm volatile ("fence" :::"memory"); } -void flush_dcache_range(unsigned long start, unsigned long end) + +__weak void flush_dcache_range(unsigned long start, unsigned long end) { - flush_dcache_all(); } void invalidate_icache_range(unsigned long start, unsigned long end) @@ -29,9 +28,8 @@ void invalidate_icache_range(unsigned long start, unsigned long end) invalidate_icache_all(); } -void invalidate_dcache_range(unsigned long start, unsigned long end) +__weak void invalidate_dcache_range(unsigned long start, unsigned long end) { - flush_dcache_all(); } void cache_flush(void) -- cgit v1.2.3