From 62a09ad53b7cb18bb47dc3c77155f56b894a6df5 Mon Sep 17 00:00:00 2001 From: Lukas Auer Date: Thu, 22 Nov 2018 11:26:23 +0100 Subject: riscv: implement the invalidate_icache_* functions Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- arch/riscv/lib/cache.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/riscv/lib/cache.c') diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index 1d67c49c2c0..d642a38a071 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -12,6 +12,16 @@ void flush_dcache_range(unsigned long start, unsigned long end) void invalidate_icache_range(unsigned long start, unsigned long end) { + /* + * RISC-V does not have an instruction for invalidating parts of the + * instruction cache. Invalidate all of it instead. + */ + invalidate_icache_all(); +} + +void invalidate_icache_all(void) +{ + asm volatile ("fence.i" ::: "memory"); } void invalidate_dcache_range(unsigned long start, unsigned long end) -- cgit v1.2.3 From 52923c6db7f00e0197ec894c8c1bb8a7681974bb Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Wed, 7 Nov 2018 09:34:06 +0800 Subject: riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen Cc: Greentime Hu --- arch/riscv/lib/cache.c | 32 +++++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 9 deletions(-) (limited to 'arch/riscv/lib/cache.c') diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index d642a38a071..ae5c60716ff 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -6,8 +6,18 @@ #include +void invalidate_icache_all(void) +{ + asm volatile ("fence.i" ::: "memory"); +} + +void flush_dcache_all(void) +{ + asm volatile ("fence" :::"memory"); +} void flush_dcache_range(unsigned long start, unsigned long end) { + flush_dcache_all(); } void invalidate_icache_range(unsigned long start, unsigned long end) @@ -19,41 +29,45 @@ void invalidate_icache_range(unsigned long start, unsigned long end) invalidate_icache_all(); } -void invalidate_icache_all(void) +void invalidate_dcache_range(unsigned long start, unsigned long end) { - asm volatile ("fence.i" ::: "memory"); + flush_dcache_all(); } -void invalidate_dcache_range(unsigned long start, unsigned long end) +void cache_flush(void) { + invalidate_icache_all(); + flush_dcache_all(); } void flush_cache(unsigned long addr, unsigned long size) { + invalidate_icache_all(); + flush_dcache_all(); } -void icache_enable(void) +__weak void icache_enable(void) { } -void icache_disable(void) +__weak void icache_disable(void) { } -int icache_status(void) +__weak int icache_status(void) { return 0; } -void dcache_enable(void) +__weak void dcache_enable(void) { } -void dcache_disable(void) +__weak void dcache_disable(void) { } -int dcache_status(void) +__weak int dcache_status(void) { return 0; } -- cgit v1.2.3