From b2c860c6dc5078c710b34a0dec9d6514cf390a85 Mon Sep 17 00:00:00 2001 From: Lukas Auer Date: Thu, 22 Nov 2018 11:26:17 +0100 Subject: riscv: fix use of incorrectly sized variables The RISC-V arch incorrectly uses 32-bit instead of 64-bit variables in several places. Fix this. In addition, BITS_PER_LONG is set to 64 on RV64I systems. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng --- arch/riscv/lib/interrupts.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/riscv/lib/interrupts.c') diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index 0a0995a7af9..62a16b4da9f 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -12,7 +12,7 @@ #include #include -static void _exit_trap(int code, uint epc, struct pt_regs *regs); +static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs); int interrupt_init(void) { @@ -34,9 +34,9 @@ int disable_interrupts(void) return 0; } -uint handle_trap(uint mcause, uint epc, struct pt_regs *regs) +ulong handle_trap(ulong mcause, ulong epc, struct pt_regs *regs) { - uint is_int; + ulong is_int; is_int = (mcause & MCAUSE_INT); if ((is_int) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) @@ -60,7 +60,7 @@ __attribute__((weak)) void timer_interrupt(struct pt_regs *regs) { } -static void _exit_trap(int code, uint epc, struct pt_regs *regs) +static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs) { static const char * const exception_code[] = { "Instruction address misaligned", @@ -70,6 +70,6 @@ static void _exit_trap(int code, uint epc, struct pt_regs *regs) "Load address misaligned" }; - printf("exception code: %d , %s , epc %08x , ra %08lx\n", + printf("exception code: %ld , %s , epc %lx , ra %lx\n", code, exception_code[code], epc, regs->ra); } -- cgit v1.2.3 From 5a441736b7dda7fd4dde0a2417aeab59a9ef9424 Mon Sep 17 00:00:00 2001 From: Lukas Auer Date: Thu, 22 Nov 2018 11:26:20 +0100 Subject: riscv: complete the list of exception codes Only the first four exception codes are defined. Add the missing exception codes from the definition in RISC-V Privileged Architecture Version 1.10. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- arch/riscv/lib/interrupts.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'arch/riscv/lib/interrupts.c') diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index 62a16b4da9f..6a12818c2b2 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -67,7 +67,18 @@ static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs) "Instruction access fault", "Illegal instruction", "Breakpoint", - "Load address misaligned" + "Load address misaligned", + "Load access fault", + "Store/AMO address misaligned", + "Store/AMO access fault", + "Environment call from U-mode", + "Environment call from S-mode", + "Reserved", + "Environment call from M-mode", + "Instruction page fault", + "Load page fault", + "Reserved", + "Store/AMO page fault", }; printf("exception code: %ld , %s , epc %lx , ra %lx\n", -- cgit v1.2.3 From e8b522b1df8b5874e08b53f6e5aef8a2c458446b Mon Sep 17 00:00:00 2001 From: Lukas Auer Date: Thu, 22 Nov 2018 11:26:21 +0100 Subject: riscv: treat undefined exception codes as reserved Undefined exception codes currently lead to an out-of-bounds array access. Prevent this by treating undefined exception codes as "reserved". Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- arch/riscv/lib/interrupts.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'arch/riscv/lib/interrupts.c') diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index 6a12818c2b2..d0d8de500ee 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -81,6 +81,10 @@ static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs) "Store/AMO page fault", }; - printf("exception code: %ld , %s , epc %lx , ra %lx\n", - code, exception_code[code], epc, regs->ra); + if (code < ARRAY_SIZE(exception_code)) { + printf("exception code: %ld , %s , epc %lx , ra %lx\n", + code, exception_code[code], epc, regs->ra); + } else { + printf("Reserved\n"); + } } -- cgit v1.2.3 From c93a1c8185e64b9571df9f7fe2c33f26cd3c41d7 Mon Sep 17 00:00:00 2001 From: Lukas Auer Date: Thu, 22 Nov 2018 11:26:22 +0100 Subject: riscv: hang on unhandled exceptions Hang on unhandled exceptions to prevent execution in a faulty state. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- arch/riscv/lib/interrupts.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/riscv/lib/interrupts.c') diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index d0d8de500ee..903a1c4cd55 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -87,4 +87,6 @@ static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs) } else { printf("Reserved\n"); } + + hang(); } -- cgit v1.2.3